clk: ast2600: Fix enabling of clocks
The struct clk_ops enable callback for the aspeed gates mixes up the set
to clear and write to set registers.
Fixes: d3d04f6c33
("clk: Add support for AST2600 SoC")
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20191016131319.31318-1-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -266,10 +266,11 @@ static int aspeed_g6_clk_enable(struct clk_hw *hw)
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/* Enable clock */
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if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
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regmap_write(gate->map, get_clock_reg(gate), clk);
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} else {
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/* Use set to clear register */
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/* Clock is clear to enable, so use set to clear register */
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regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
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} else {
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/* Clock is set to enable, so use write to set register */
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regmap_write(gate->map, get_clock_reg(gate), clk);
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}
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if (gate->reset_idx >= 0) {
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