ARM64: DT: Hisilicon SoC DT updates for 4.20
- Add missing clocks for Hi6220 - Switch to updated coresight bindings for Hi6220 - Add DT bindings and support for Hi3670 SoC and HiKey970 board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbpPu0AAoJEAvIV27ZiWZcOU8P/RrzQOp1PKIQwmwaAW6Ra820 urcpY1bhYUYXrCA60BiTy9hzjqEi2kWljEcmoQoEIpF/I8TujIrUOX9ybvuexewP yTsdNmm5HidOm4e02Tk95ygSuRNyHkLexCe0adzfK0eTMQx7SPgcBMqEys++oZw+ +vqyj2HxIPOp9fs71aqhPEjK1c0yePozk//Ss2tW5WZh5LGoGbbaZvU/EmokY+f3 uNQn6y+/sTDxnVqew4lVHe1JpV9nRfFhpbR5/Ggj5nzcGAea89GevS5l9mV3l63e blAPzOsihUyBgmqfM+HOGEu/ExWqL7bI6ia1j8qGzDUZUP5oOtXnw2wXwbHw0SiR DTK2joRiAIA/8W01iCBiNZtWzXPjQvafoJilXXwI7TxdT70WPpFM9xcMSx5kXbXq sN0y/QmxD6KV6yYmizKgB8TkrLSNH+jYLrFryuR2URCrADT0p50k5Fn5EI07oeaE zr3vxU06vN2D0CMavLBvn1r+HwNwquaz35kBoXNdGZKfoi7SJ0Y70nfDYJj6tzNU aU3a5J3eV26sFyIuKJxLBjhYWzv6I/3LQ63OWgnjjYzwcRy8fkWN7qlZjxuWYBO9 HQgnSO1/+vTM6zzb6AHS+Y1qY5F5EMLz9DSA+R6jtH3qr2qRAAed+4DkurP3NNMX S+rdLQrm4jeg4yjwk59i =64/5 -----END PGP SIGNATURE----- Merge tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi into next/dt ARM64: DT: Hisilicon SoC DT updates for 4.20 - Add missing clocks for Hi6220 - Switch to updated coresight bindings for Hi6220 - Add DT bindings and support for Hi3670 SoC and HiKey970 board * tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi: arm64: dts: Add devicetree support for HiKey970 board dt-bindings: arm: hisilicon: Add binding for HiKey970 board arm64: dts: Add devicetree for Hisilicon Hi3670 SoC dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC arm64: dts: hi6220: Update coresight bindings for hardware ports arm64: dts: hisilicon: Add missing clocks property for CPUs Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
42724dd893
@ -8,6 +8,14 @@ HiKey960 Board
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Required root node properties:
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- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
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Hi3670 SoC
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Required root node properties:
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- compatible = "hisilicon,hi3670";
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HiKey970 Board
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Required root node properties:
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- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
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Hi3798cv200 SoC
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Required root node properties:
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- compatible = "hisilicon,hi3798cv200";
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
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dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
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35
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
Normal file
35
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
Normal file
@ -0,0 +1,35 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Hisilicon HiKey970 Development Board
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*
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* Copyright (C) 2016, Hisilicon Ltd.
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* Copyright (C) 2018, Linaro Ltd.
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*
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*/
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/dts-v1/;
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#include "hi3670.dtsi"
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/ {
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model = "HiKey970";
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compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
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aliases {
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serial6 = &uart6; /* console UART */
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};
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chosen {
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stdout-path = "serial6:115200n8";
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};
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memory@0 {
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device_type = "memory";
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/* expect bootloader to fill in this region */
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reg = <0x0 0x0 0x0 0x0>;
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};
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};
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&uart6 {
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status = "okay";
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};
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162
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
Normal file
162
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
Normal file
@ -0,0 +1,162 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Hisilicon Hi3670 SoC
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*
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* Copyright (C) 2016, Hisilicon Ltd.
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* Copyright (C) 2018, Linaro Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "hisilicon,hi3670";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x101>;
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enable-method = "psci";
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x102>;
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enable-method = "psci";
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x103>;
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enable-method = "psci";
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};
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};
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gic: interrupt-controller@e82b0000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
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<0x0 0xe82b2000 0 0x2000>, /* GICC */
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<0x0 0xe82b4000 0 0x2000>, /* GICH */
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<0x0 0xe82b6000 0 0x2000>; /* GICV */
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <1920000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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uart6_clk: clk_19_2M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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uart6: serial@fff32000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfff32000 0x0 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart6_clk &uart6_clk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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@ -20,22 +20,18 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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out-ports {
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port {
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soc_funnel_out: endpoint {
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remote-endpoint =
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<&etf_in>;
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};
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};
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};
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port@1 {
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reg = <0>;
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in-ports {
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port {
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soc_funnel_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&acpu_funnel_out>;
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};
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@ -49,21 +45,17 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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in-ports {
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port {
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etf_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&soc_funnel_out>;
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};
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};
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};
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port@1 {
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reg = <0>;
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out-ports {
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port {
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etf_out: endpoint {
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remote-endpoint =
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<&replicator_in>;
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@ -77,20 +69,20 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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in-ports {
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port {
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&etf_out>;
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};
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};
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};
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port@1 {
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint =
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@ -98,7 +90,7 @@
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};
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};
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port@2 {
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint =
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@ -114,14 +106,9 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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in-ports {
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port {
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etr_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&replicator_out0>;
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};
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@ -135,14 +122,9 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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in-ports {
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port {
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&replicator_out1>;
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};
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@ -156,85 +138,78 @@
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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out-ports {
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port {
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acpu_funnel_out: endpoint {
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remote-endpoint =
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<&soc_funnel_in>;
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};
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};
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};
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port@1 {
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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acpu_funnel_in0: endpoint {
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slave-mode;
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remote-endpoint =
|
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<&etm0_out>;
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};
|
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};
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port@2 {
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port@1 {
|
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reg = <1>;
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acpu_funnel_in1: endpoint {
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slave-mode;
|
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remote-endpoint =
|
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<&etm1_out>;
|
||||
};
|
||||
};
|
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port@3 {
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||||
port@2 {
|
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reg = <2>;
|
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acpu_funnel_in2: endpoint {
|
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slave-mode;
|
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remote-endpoint =
|
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<&etm2_out>;
|
||||
};
|
||||
};
|
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|
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port@4 {
|
||||
port@3 {
|
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reg = <3>;
|
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acpu_funnel_in3: endpoint {
|
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slave-mode;
|
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remote-endpoint =
|
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<&etm3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
acpu_funnel_in4: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
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<&etm4_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
acpu_funnel_in5: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@7 {
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
acpu_funnel_in6: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm6_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
acpu_funnel_in7: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint =
|
||||
<&etm7_out>;
|
||||
};
|
||||
@ -251,10 +226,12 @@
|
||||
|
||||
cpu = <&cpu0>;
|
||||
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in0>;
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -268,10 +245,12 @@
|
||||
|
||||
cpu = <&cpu1>;
|
||||
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in1>;
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -285,10 +264,12 @@
|
||||
|
||||
cpu = <&cpu2>;
|
||||
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in2>;
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -302,10 +283,12 @@
|
||||
|
||||
cpu = <&cpu3>;
|
||||
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in3>;
|
||||
out-ports {
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -319,10 +302,12 @@
|
||||
|
||||
cpu = <&cpu4>;
|
||||
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in4>;
|
||||
out-ports {
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -336,10 +321,12 @@
|
||||
|
||||
cpu = <&cpu5>;
|
||||
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in5>;
|
||||
out-ports {
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -353,10 +340,12 @@
|
||||
|
||||
cpu = <&cpu6>;
|
||||
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in6>;
|
||||
out-ports {
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -370,10 +359,12 @@
|
||||
|
||||
cpu = <&cpu7>;
|
||||
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in7>;
|
||||
out-ports {
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&acpu_funnel_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -99,6 +99,7 @@
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -111,6 +112,7 @@
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -123,6 +125,7 @@
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -135,6 +138,7 @@
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER1_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -147,6 +151,7 @@
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER1_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -159,6 +164,7 @@
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER1_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
@ -171,6 +177,7 @@
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER1_L2>;
|
||||
clocks = <&stub_clock 0>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user