forked from Minki/linux
clk: mvebu: add clock support for Armada 375
Add the clock support for the new SoC Armada 375: core clocks and gating clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Gregory CLEMENT
Jason Cooper
parent
e4aec65c86
commit
41d3c64f8c
@ -13,6 +13,10 @@ config ARMADA_370_CLK
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select MVEBU_CLK_CPU
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select MVEBU_CLK_COREDIV
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config ARMADA_375_CLK
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bool
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select MVEBU_CLK_COMMON
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config ARMADA_XP_CLK
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bool
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select MVEBU_CLK_COMMON
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@ -3,6 +3,7 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
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obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
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obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
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obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
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obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
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obj-$(CONFIG_DOVE_CLK) += dove.o
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obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
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184
drivers/clk/mvebu/armada-375.c
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184
drivers/clk/mvebu/armada-375.c
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@ -0,0 +1,184 @@
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/*
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* Marvell Armada 375 SoC clocks
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* Core Clocks
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*/
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/*
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* For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are
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* all modified at the same time, and not separately as for the Armada
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* 370 or the Armada XP SoCs.
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*
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* SAR0[21:17] : CPU frequency DDR frequency L2 frequency
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* 6 = 400 MHz 400 MHz 200 MHz
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* 15 = 600 MHz 600 MHz 300 MHz
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* 21 = 800 MHz 534 MHz 400 MHz
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* 25 = 1000 MHz 500 MHz 500 MHz
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* others reserved.
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*
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* SAR0[22] : TCLK frequency
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* 0 = 166 MHz
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* 1 = 200 MHz
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*/
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#define SAR1_A375_TCLK_FREQ_OPT 22
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#define SAR1_A375_TCLK_FREQ_OPT_MASK 0x1
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#define SAR1_A375_CPU_DDR_L2_FREQ_OPT 17
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#define SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
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static const u32 armada_375_tclk_frequencies[] __initconst = {
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166000000,
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200000000,
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};
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static u32 __init armada_375_get_tclk_freq(void __iomem *sar)
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{
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u8 tclk_freq_select;
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tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) &
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SAR1_A375_TCLK_FREQ_OPT_MASK);
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return armada_375_tclk_frequencies[tclk_freq_select];
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}
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static const u32 armada_375_cpu_frequencies[] __initconst = {
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0, 0, 0, 0, 0, 0,
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400000000,
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0, 0, 0, 0, 0, 0, 0, 0,
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600000000,
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0, 0, 0, 0, 0,
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800000000,
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0, 0, 0,
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1000000000,
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};
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static u32 __init armada_375_get_cpu_freq(void __iomem *sar)
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{
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u8 cpu_freq_select;
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cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
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SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
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if (cpu_freq_select >= ARRAY_SIZE(armada_375_cpu_frequencies)) {
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pr_err("Selected CPU frequency (%d) unsupported\n",
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cpu_freq_select);
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return 0;
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} else
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return armada_375_cpu_frequencies[cpu_freq_select];
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}
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enum { A375_CPU_TO_DDR, A375_CPU_TO_L2 };
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static const struct coreclk_ratio armada_375_coreclk_ratios[] __initconst = {
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{ .id = A375_CPU_TO_L2, .name = "l2clk" },
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{ .id = A375_CPU_TO_DDR, .name = "ddrclk" },
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};
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static const int armada_375_cpu_l2_ratios[32][2] __initconst = {
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {1, 2}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 2},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {1, 2}, {0, 1}, {0, 1},
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{0, 1}, {1, 2}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int armada_375_cpu_ddr_ratios[32][2] __initconst = {
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {1, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {2, 3},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {2, 3}, {0, 1}, {0, 1},
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{0, 1}, {1, 2}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static void __init armada_375_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
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SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
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switch (id) {
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case A375_CPU_TO_L2:
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*mult = armada_375_cpu_l2_ratios[opt][0];
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*div = armada_375_cpu_l2_ratios[opt][1];
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break;
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case A375_CPU_TO_DDR:
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*mult = armada_375_cpu_ddr_ratios[opt][0];
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*div = armada_375_cpu_ddr_ratios[opt][1];
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break;
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}
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}
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static const struct coreclk_soc_desc armada_375_coreclks = {
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.get_tclk_freq = armada_375_get_tclk_freq,
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.get_cpu_freq = armada_375_get_cpu_freq,
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.get_clk_ratio = armada_375_get_clk_ratio,
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.ratios = armada_375_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(armada_375_coreclk_ratios),
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};
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static void __init armada_375_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &armada_375_coreclks);
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}
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CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",
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armada_375_coreclk_init);
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc armada_375_gating_desc[] __initconst = {
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{ "mu", NULL, 2 },
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{ "pp", NULL, 3 },
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{ "ptp", NULL, 4 },
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{ "pex0", NULL, 5 },
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{ "pex1", NULL, 6 },
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{ "audio", NULL, 8 },
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{ "nd_clk", "nand", 11 },
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{ "sata0_link", "sata0_core", 14 },
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{ "sata0_core", NULL, 15 },
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{ "usb3", NULL, 16 },
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{ "sdio", NULL, 17 },
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{ "usb", NULL, 18 },
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{ "gop", NULL, 19 },
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{ "sata1_link", "sata1_core", 20 },
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{ "sata1_core", NULL, 21 },
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{ "xor0", NULL, 22 },
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{ "xor1", NULL, 23 },
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{ "copro", NULL, 24 },
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{ "tdm", NULL, 25 },
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{ "crypto0_enc", NULL, 28 },
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{ "crypto0_core", NULL, 29 },
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{ "crypto1_enc", NULL, 30 },
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{ "crypto1_core", NULL, 31 },
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{ }
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};
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static void __init armada_375_clk_gating_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, armada_375_gating_desc);
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}
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CLK_OF_DECLARE(armada_375_clk_gating, "marvell,armada-375-gating-clock",
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armada_375_clk_gating_init);
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