forked from Minki/linux
Merge tag 'drm-intel-fixes-2017-08-16' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes
drm/i915 fixes for v4.13-rc6 "Chris' "drm/i915: Perform an invalidate prior to executing golden renderstate" and Daniel's "drm/i915: Avoid the gpu reset vs. modeset deadlock" seem like the most important ones. * tag 'drm-intel-fixes-2017-08-16' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Avoid the gpu reset vs. modeset deadlock drm/i915: Suppress switch_mm emission between the same aliasing_ppgtt drm/i915: Return correct EDP voltage swing table for 0.85V drm/i915/cnl: Add slice and subslice information to debugfs. drm/i915: Perform an invalidate prior to executing golden renderstate drm/i915: remove unused function declaration
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commit
41d31b5fd2
@ -4580,7 +4580,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
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sseu->slice_mask |= BIT(s);
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if (IS_GEN9_BC(dev_priv))
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
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sseu->subslice_mask =
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INTEL_INFO(dev_priv)->sseu.subslice_mask;
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@ -688,19 +688,19 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
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}
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static bool
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needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
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struct intel_engine_cs *engine,
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struct i915_gem_context *to)
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needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
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{
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struct i915_gem_context *from = engine->legacy_active_context;
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if (!ppgtt)
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return false;
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/* Always load the ppgtt on first use */
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if (!engine->legacy_active_context)
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if (!from)
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return true;
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/* Same context without new entries, skip */
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if (engine->legacy_active_context == to &&
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if ((!from->ppgtt || from->ppgtt == ppgtt) &&
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!(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
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return false;
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@ -744,7 +744,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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if (skip_rcs_switch(ppgtt, engine, to))
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return 0;
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if (needs_pd_load_pre(ppgtt, engine, to)) {
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if (needs_pd_load_pre(ppgtt, engine)) {
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/* Older GENs and non render rings still want the load first,
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* "PP_DCLV followed by PP_DIR_BASE register through Load
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* Register Immediate commands in Ring Buffer before submitting
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@ -841,7 +841,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
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struct i915_hw_ppgtt *ppgtt =
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to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
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if (needs_pd_load_pre(ppgtt, engine, to)) {
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if (needs_pd_load_pre(ppgtt, engine)) {
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int ret;
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trace_switch_mm(engine, to);
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@ -852,6 +852,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
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ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
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}
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engine->legacy_active_context = to;
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return 0;
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}
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@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req)
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goto err_unpin;
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}
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ret = req->engine->emit_flush(req, EMIT_INVALIDATE);
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if (ret)
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goto err_unpin;
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ret = req->engine->emit_bb_start(req,
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so->batch_offset, so->batch_size,
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I915_DISPATCH_SECURE);
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@ -1762,7 +1762,7 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
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if (dev_priv->vbt.edp.low_vswing) {
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if (voltage == VOLTAGE_INFO_0_85V) {
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*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
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return cnl_ddi_translations_dp_0_85V;
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return cnl_ddi_translations_edp_0_85V;
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} else if (voltage == VOLTAGE_INFO_0_95V) {
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*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
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return cnl_ddi_translations_edp_0_95V;
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@ -3485,6 +3485,13 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
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!gpu_reset_clobbers_display(dev_priv))
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return;
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/* We have a modeset vs reset deadlock, defensively unbreak it.
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*
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* FIXME: We can do a _lot_ better, this is just a first iteration.
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*/
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i915_gem_set_wedged(dev_priv);
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DRM_DEBUG_DRIVER("Wedging GPU to avoid deadlocks with pending modeset updates\n");
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/*
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* Need mode_config.mutex so that we don't
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* trample ongoing ->detect() and whatnot.
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@ -63,7 +63,6 @@ enum {
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};
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/* Logical Rings */
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void intel_logical_ring_stop(struct intel_engine_cs *engine);
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int logical_render_ring_init(struct intel_engine_cs *engine);
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int logical_xcs_ring_init(struct intel_engine_cs *engine);
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