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mlxsw: reg: Add Monitoring Global Configuration Register

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This register serves to configure global parameters of certain
monitoring operations. The following patches will use it to configure
that when PTP timestamps are delivered through the PTP FIFO traps, the
FIFO in question is cleared as well.

Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Petr Machata 2019-06-30 09:04:48 +03:00 committed by David S. Miller
parent 98b9028ea5
commit 41ce78b92e
1 changed files with 27 additions and 0 deletions
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27
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -9148,6 +9148,32 @@ static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
}
/* MOGCR - Monitoring Global Configuration Register
* ------------------------------------------------
*/
#define MLXSW_REG_MOGCR_ID 0x9086
#define MLXSW_REG_MOGCR_LEN 0x20
MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
/* reg_mogcr_ptp_iftc
* PTP Ingress FIFO Trap Clear
* The PTP_ING_FIFO trap provides MTPPTR with clr according
* to this value. Default 0.
* Reserved when IB switches and when SwitchX/-2, Spectrum-2
* Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
/* reg_mogcr_ptp_eftc
* PTP Egress FIFO Trap Clear
* The PTP_EGR_FIFO trap provides MTPPTR with clr according
* to this value. Default 0.
* Reserved when IB switches and when SwitchX/-2, Spectrum-2
* Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
/* MTPPPC - Time Precision Packet Port Configuration
* -------------------------------------------------
* This register serves for configuration of which PTP messages should be
@ -10400,6 +10426,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(mcda),
MLXSW_REG(mgpc),
MLXSW_REG(mprs),
MLXSW_REG(mogcr),
MLXSW_REG(mtpppc),
MLXSW_REG(mtpptr),
MLXSW_REG(mtptpt),