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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

Browse Source 
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] N32 needs to use the compat version of sys_nfsservctl.
  [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
  [MIPS] Sibyte: Fix name of clocksource.
  [MIPS] SNI: s/achknowledge/acknowledge/
  [MIPS] Makefile: Fix canonical system names
  [MIPS] vpe: handle halting TCs in an errata safe way.
  [MIPS] Sibyte: Stop timers before programming next even.
  [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.
  [MIPS] Lasat: Fix overlap of interrupt number ranges.
  [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1
  [MIPS] Fix shadow register support.
  [MIPS] Change get_cycles to always return 0.
  [MIPS] Fix typo in R3000 TRACE_IRQFLAGS code
  [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.
  [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz
  [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.
  [MIPS] Sibyte: pin timer interrupt to their cores.
  [MIPS] Qemu: Add early printk, your friend in a cold night.
  [MIPS] Convert reference to mem_map to pfn_to_page().
  [MIPS] Sibyte: resurrect old cache hack.
This commit is contained in:
Linus Torvalds 2007-11-15 16:08:49 -08:00
commit 40787d0099
31 changed files with 157 additions and 144 deletions
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11
arch/mips/Kconfig
View File

@ -361,10 +361,10 @@ config QEMU
select PCSPEAKER
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select ARCH_SPARSEMEM_ENABLE
select GENERIC_HARDIRQS_NO__DO_IRQ
select NR_CPUS_DEFAULT_1
select SYS_SUPPORTS_SMP
@ -1409,7 +1409,6 @@ config MIPS_MT_SMP
depends on SYS_SUPPORTS_MULTITHREADING
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
select NR_CPUS_DEFAULT_2
select SMP
@ -1426,7 +1425,6 @@ config MIPS_MT_SMTC
select GENERIC_CLOCKEVENTS_BROADCAST
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
select NR_CPUS_DEFAULT_8
select SMP
@ -1453,7 +1451,6 @@ config MIPS_VPE_LOADER
depends on SYS_SUPPORTS_MULTITHREADING
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
help
Includes a loader for loading an elf relocatable object
@ -1582,12 +1579,6 @@ config CPU_MIPSR2_IRQ_VI
config CPU_MIPSR2_IRQ_EI
bool
#
# Shadow registers are an R2 feature
#
config CPU_MIPSR2_SRS
bool
config CPU_HAS_SYNC
bool
depends on !CPU_R3000

2
arch/mips/Makefile
View File

@ -44,7 +44,7 @@ endif
ifneq ($(SUBARCH),$(ARCH))
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux- $(tool-archpref)-gnu-linux- $(tool-archpref)-unknown-gnu-linux-)
CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux- $(tool-archpref)-linux-gnu- $(tool-archpref)-unknown-linux-gnu-)
endif
endif

6
arch/mips/kernel/cevt-bcm1480.c
View File

@ -75,6 +75,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
__raw_writeq(0, cfg);
__raw_writeq(delta - 1, init);
__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
@ -122,7 +123,7 @@ void __cpuinit sb1480_clockevent_init(void)
CLOCK_EVT_FEAT_ONESHOT;
clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
cd->min_delta_ns = clockevent_delta2ns(1, cd);
cd->min_delta_ns = clockevent_delta2ns(2, cd);
cd->rating = 200;
cd->irq = irq;
cd->cpumask = cpumask_of_cpu(cpu);
@ -143,7 +144,10 @@ void __cpuinit sb1480_clockevent_init(void)
action->handler = sibyte_counter_handler;
action->flags = IRQF_DISABLED | IRQF_PERCPU;
action->mask = cpumask_of_cpu(cpu);
action->name = name;
action->dev_id = cd;
irq_set_affinity(irq, cpumask_of_cpu(cpu));
setup_irq(irq, action);
}

6
arch/mips/kernel/cevt-sb1250.c
View File

@ -73,6 +73,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
__raw_writeq(0, cfg);
__raw_writeq(delta - 1, init);
__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
@ -121,7 +122,7 @@ void __cpuinit sb1250_clockevent_init(void)
CLOCK_EVT_FEAT_ONESHOT;
clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
cd->min_delta_ns = clockevent_delta2ns(1, cd);
cd->min_delta_ns = clockevent_delta2ns(2, cd);
cd->rating = 200;
cd->irq = irq;
cd->cpumask = cpumask_of_cpu(cpu);
@ -142,7 +143,10 @@ void __cpuinit sb1250_clockevent_init(void)
action->handler = sibyte_counter_handler;
action->flags = IRQF_DISABLED | IRQF_PERCPU;
action->mask = cpumask_of_cpu(cpu);
action->name = name;
action->dev_id = cd;
irq_set_affinity(irq, cpumask_of_cpu(cpu));
setup_irq(irq, action);
}

5
arch/mips/kernel/cpu-probe.c
View File

@ -943,6 +943,11 @@ __init void cpu_probe(void)
}
__cpu_name[cpu] = cpu_to_name(c);
if (cpu_has_mips_r2)
c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
else
c->srsets = 1;
}
__init void cpu_report(void)

2
arch/mips/kernel/csrc-sb1250.c
View File

@ -43,7 +43,7 @@ static cycle_t sb1250_hpt_read(void)
}
struct clocksource bcm1250_clocksource = {
.name = "MIPS",
.name = "bcm1250-counter-3",
.rating = 200,
.read = sb1250_hpt_read,
.mask = CLOCKSOURCE_MASK(23),

2
arch/mips/kernel/genex.S
View File

@ -146,7 +146,7 @@ NESTED(handle_int, PT_SIZE, sp)
and k0, ST0_IEP
bnez k0, 1f
mfc0 k0, EP0_EPC
mfc0 k0, CP0_EPC
.set noreorder
j k0
rfe

2
arch/mips/kernel/irq-rm7000.c
View File

@ -44,5 +44,5 @@ void __init rm7k_cpu_irq_init(void)
for (i = base; i < base + 4; i++)
set_irq_chip_and_handler(i, &rm7k_irq_controller,
handle_level_irq);
handle_percpu_irq);
}

2
arch/mips/kernel/irq-rm9000.c
View File

@ -104,5 +104,5 @@ void __init rm9k_cpu_irq_init(void)
rm9000_perfcount_irq = base + 1;
set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
handle_level_irq);
handle_percpu_irq);
}

2
arch/mips/kernel/irq_cpu.c
View File

@ -116,5 +116,5 @@ void __init mips_cpu_irq_init(void)
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
handle_level_irq);
handle_percpu_irq);
}

2
arch/mips/kernel/proc.c
View File

@ -60,6 +60,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
cpu_has_dsp ? " dsp" : "",
cpu_has_mipsmt ? " mt" : ""
);
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");

2
arch/mips/kernel/scall64-n32.S
View File

@ -293,7 +293,7 @@ EXPORT(sysn32_call_table)
PTR sys_ni_syscall /* 6170, was get_kernel_syms */
PTR sys_ni_syscall /* was query_module */
PTR sys_quotactl
PTR sys_nfsservctl
PTR compat_sys_nfsservctl
PTR sys_ni_syscall /* res. for getpmsg */
PTR sys_ni_syscall /* 6175 for putpmsg */
PTR sys_ni_syscall /* res. for afs_syscall */

68
arch/mips/kernel/traps.c
View File

@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
return (void *)old_handler;
}
#ifdef CONFIG_CPU_MIPSR2_SRS
/*
* MIPSR2 shadow register set allocation
* FIXME: SMP...
*/
static struct shadow_registers {
/*
* Number of shadow register sets supported
*/
unsigned long sr_supported;
/*
* Bitmap of allocated shadow registers
*/
unsigned long sr_allocated;
} shadow_registers;
static void mips_srs_init(void)
{
shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
printk(KERN_INFO "%ld MIPSR2 register sets available\n",
shadow_registers.sr_supported);
shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
}
int mips_srs_max(void)
{
return shadow_registers.sr_supported;
}
int mips_srs_alloc(void)
{
struct shadow_registers *sr = &shadow_registers;
int set;
again:
set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
if (set >= sr->sr_supported)
return -1;
if (test_and_set_bit(set, &sr->sr_allocated))
goto again;
return set;
}
void mips_srs_free(int set)
{
struct shadow_registers *sr = &shadow_registers;
clear_bit(set, &sr->sr_allocated);
}
static asmlinkage void do_default_vi(void)
{
show_regs(get_irq_regs());
@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
{
unsigned long handler;
unsigned long old_handler = vi_handlers[n];
int srssets = current_cpu_data.srsets;
u32 *w;
unsigned char *b;
@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
if (srs >= mips_srs_max())
if (srs >= srssets)
panic("Shadow register set %d not supported", srs);
if (cpu_has_veic) {
@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
board_bind_eic_interrupt(n, srs);
} else if (cpu_has_vint) {
/* SRSMap is only defined if shadow sets are implemented */
if (mips_srs_max() > 1)
if (srssets > 1)
change_c0_srsmap(0xf << n*4, srs << n*4);
}
@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
return set_vi_srs_handler(n, addr, 0);
}
#else
static inline void mips_srs_init(void)
{
}
#endif /* CONFIG_CPU_MIPSR2_SRS */
/*
* This is used by native signal handling
*/
@ -1503,8 +1443,6 @@ void __init trap_init(void)
else
ebase = CAC_BASE;
mips_srs_init();
per_cpu_trap_init();
/*

14
arch/mips/kernel/vpe.c
View File

@ -1003,6 +1003,7 @@ static void cleanup_tc(struct tc *tc)
write_tc_c0_tcstatus(tmp);
write_tc_c0_tchalt(TCHALT_H);
mips_ihb();
/* bind it to anything other than VPE1 */
// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
@ -1235,9 +1236,12 @@ int vpe_free(vpe_handle vpe)
settc(t->index);
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
/* mark the TC unallocated and halt'ed */
write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
/* halt the TC */
write_tc_c0_tchalt(TCHALT_H);
mips_ihb();
/* mark the TC unallocated */
write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
v->state = VPE_STATE_UNUSED;
@ -1533,14 +1537,16 @@ static int __init vpe_module_init(void)
t->pvpe = get_vpe(0); /* set the parent vpe */
}
/* halt the TC */
write_tc_c0_tchalt(TCHALT_H);
mips_ihb();
tmp = read_tc_c0_tcstatus();
/* mark not activated and not dynamically allocatable */
tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
tmp |= TCSTATUS_IXMT; /* interrupt exempt */
write_tc_c0_tcstatus(tmp);
write_tc_c0_tchalt(TCHALT_H);
}
}

22
arch/mips/lasat/interrupt.c
View File

@ -19,17 +19,14 @@
* Lasat boards.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
#include <asm/lasat/lasatint.h>
#include <asm/time.h>
#include <asm/gdb-stub.h>
#include <irq.h>
static volatile int *lasat_int_status;
static volatile int *lasat_int_mask;
@ -97,12 +94,18 @@ asmlinkage void plat_irq_dispatch(void)
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status) {
irq = LASATINT_BASE + ls1bit32(int_status);
irq = LASAT_IRQ_BASE + ls1bit32(int_status);
do_IRQ(irq);
}
}
static struct irqaction cascade = {
.handler = no_action,
.mask = CPU_MASK_NONE,
.name = "cascade",
};
void __init arch_init_irq(void)
{
int i;
@ -127,6 +130,9 @@ void __init arch_init_irq(void)
}
mips_cpu_irq_init();
for (i = LASATINT_BASE; i <= LASATINT_END; i++)
for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
setup_irq(LASAT_CASCADE_IRQ, &cascade);
}

7
arch/mips/mm/c-r4k.c
View File

@ -7,6 +7,7 @@
* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/highmem.h>
#include <linux/kernel.h>
@ -507,7 +508,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
static void r4k_flush_data_cache_page(unsigned long addr)
{
r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
if (in_atomic())
local_r4k_flush_data_cache_page((void *)addr);
else
r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
1, 1);
}
struct flush_icache_range_args {

6
arch/mips/mm/cerr-sb1.c
View File

@ -154,7 +154,7 @@ static void check_bus_watcher(void)
if (status & ~(1UL << 31)) {
l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
#ifdef DUMP_L2_ECC_TAG_ON_ERROR
l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG);
l2_tag = in64(IOADDR(A_L2_ECC_TAG));
#endif
memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
@ -183,9 +183,9 @@ asmlinkage void sb1_cache_error(void)
#ifdef CONFIG_SIBYTE_BW_TRACE
/* Freeze the trace buffer now */
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
#else
csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
#endif
printk("Trace buffer frozen\n");
#endif

2
arch/mips/mm/init.c
View File

@ -426,7 +426,7 @@ void __init mem_init(void)
#ifdef CONFIG_HIGHMEM
for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
struct page *page = mem_map + tmp;
struct page *page = pfn_to_page(tmp);
if (!page_is_ram(tmp)) {
SetPageReserved(page);

23
arch/mips/pci/fixup-sni.c
View File

@ -113,6 +113,16 @@ static char irq_tab_pcit[13][5] __initdata = {
{ 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
};
static char irq_tab_pcit_cplus[13][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
{ 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
{ 0, 0, 0, 0, 0 }, /* PCI-EISA */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
{ 0, INTB, INTC, INTD, INTA }, /* fixup */
};
static inline int is_rm300_revd(void)
{
unsigned char csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
@ -123,8 +133,19 @@ static inline int is_rm300_revd(void)
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
switch (sni_brd_type) {
case SNI_BRD_PCI_TOWER:
case SNI_BRD_PCI_TOWER_CPLUS:
if (slot == 4) {
/*
* SNI messed up interrupt wiring for onboard
* PCI bus 1; we need to fix this up here
*/
while (dev && dev->bus->number != 1)
dev = dev->bus->self;
if (dev && dev->devfn >= PCI_DEVFN(4, 0))
slot = 5;
}
return irq_tab_pcit_cplus[slot][pin];
case SNI_BRD_PCI_TOWER:
return irq_tab_pcit[slot][pin];
case SNI_BRD_PCI_MTOWER:

32
arch/mips/pci/pci-lasat.c
View File

@ -5,12 +5,14 @@
*
* Copyright (C) 2000, 2001, 04 Keith M Wesolowski
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/lasat/lasatint.h>
#include <irq.h>
extern struct pci_ops nile4_pci_ops;
extern struct pci_ops gt64xxx_pci0_ops;
@ -55,15 +57,15 @@ static int __init lasat_pci_setup(void)
arch_initcall(lasat_pci_setup);
#define LASATINT_ETH1 (LASATINT_BASE + 0)
#define LASATINT_ETH0 (LASATINT_BASE + 1)
#define LASATINT_HDC (LASATINT_BASE + 2)
#define LASATINT_COMP (LASATINT_BASE + 3)
#define LASATINT_HDLC (LASATINT_BASE + 4)
#define LASATINT_PCIA (LASATINT_BASE + 5)
#define LASATINT_PCIB (LASATINT_BASE + 6)
#define LASATINT_PCIC (LASATINT_BASE + 7)
#define LASATINT_PCID (LASATINT_BASE + 8)
#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
@ -71,13 +73,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
case 1:
case 2:
case 3:
return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
case 4:
return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
case 5:
return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
case 6:
return LASATINT_HDC; /* IDE controller */
return LASAT_IRQ_HDC; /* IDE controller */
default:
return 0xff; /* Illegal */
}

1
arch/mips/pci/pci-vr41xx.c
View File

@ -154,6 +154,7 @@ static int __init vr41xx_pciu_init(void)
pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
else {
printk(KERN_ERR "PCI Clock is over 33MHz.\n");
iounmap(pciu_base);
return -EINVAL;
}

3
arch/mips/qemu/Makefile
View File

@ -4,6 +4,7 @@
obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
obj-$(CONFIG_SMP) += q-smp.o
obj-$(CONFIG_EARLY_PRINTK) += q-console.o
obj-$(CONFIG_SMP) += q-smp.o
EXTRA_CFLAGS += -Werror

26
arch/mips/qemu/q-console.c Normal file
View File

@ -0,0 +1,26 @@
#include <linux/console.h>
#include <linux/init.h>
#include <linux/serial_reg.h>
#include <asm/io.h>
#define PORT(offset) (0x3f8 + (offset))
static inline unsigned int serial_in(int offset)
{
return inb(PORT(offset));
}
static inline void serial_out(int offset, int value)
{
outb(value, PORT(offset));
}
int prom_putchar(char c)
{
while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
;
serial_out(UART_TX, c);
return 1;
}

6
arch/mips/qemu/q-firmware.c
View File

@ -2,6 +2,9 @@
#include <linux/string.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#define QEMU_PORT_BASE 0xb4000000
void __init prom_init(void)
{
@ -15,4 +18,7 @@ void __init prom_init(void)
} else {
add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
}
set_io_port_base(QEMU_PORT_BASE);
}

3
arch/mips/qemu/q-setup.c
View File

@ -6,8 +6,6 @@
extern void qemu_reboot_setup(void);
#define QEMU_PORT_BASE 0xb4000000
const char *get_system_type(void)
{
return "Qemu";
@ -20,6 +18,5 @@ void __init plat_time_init(void)
void __init plat_mem_setup(void)
{
set_io_port_base(QEMU_PORT_BASE);
qemu_reboot_setup();
}

21
arch/mips/sibyte/bcm1480/irq.c
View File

@ -370,11 +370,11 @@ void __init arch_init_irq(void)
#endif
/* Setup uart 1 settings, mapper */
/* QQQ FIXME */
__raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
__raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
__raw_writeq(IMR_IP6_VAL,
IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(kgdb_irq<<3));
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(kgdb_irq << 3)));
bcm1480_unmask_irq(0, kgdb_irq);
#ifdef CONFIG_GDB_CONSOLE
@ -412,18 +412,6 @@ static void bcm1480_kgdb_interrupt(void)
extern void bcm1480_mailbox_interrupt(void);
static inline void dispatch_ip4(void)
{
int cpu = smp_processor_id();
int irq = K_BCM1480_INT_TIMER_0 + cpu;
/* Reset the timer */
__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
do_IRQ(irq);
}
static inline void dispatch_ip2(void)
{
unsigned long long mask_h, mask_l;
@ -451,6 +439,7 @@ static inline void dispatch_ip2(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int cpu = smp_processor_id();
unsigned int pending;
#ifdef CONFIG_SIBYTE_BCM1480_PROF
@ -467,7 +456,7 @@ asmlinkage void plat_irq_dispatch(void)
#endif
if (pending & CAUSEF_IP4)
dispatch_ip4();
do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
#ifdef CONFIG_SMP
else if (pending & CAUSEF_IP3)
bcm1480_mailbox_interrupt();

2
arch/mips/sni/pcimt.c
View File

@ -244,7 +244,7 @@ static void pcimt_hwint1(void)
if (pend & IT_EISA) {
int irq;
/*
* Note: ASIC PCI's builtin interrupt achknowledge feature is
* Note: ASIC PCI's builtin interrupt acknowledge feature is
* broken. Using it may result in loss of some or all i8259
* interrupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
*/

1
include/asm-mips/cpu-info.h
View File

@ -54,6 +54,7 @@ struct cpuinfo_mips {
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
#if defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered

5
include/asm-mips/lasat/lasatint.h
View File

@ -1,11 +1,6 @@
#ifndef __ASM_LASAT_LASATINT_H
#define __ASM_LASAT_LASATINT_H
#include <linux/irq.h>
#define LASATINT_BASE MIPS_CPU_IRQ_BASE
#define LASATINT_END (LASATINT_BASE + 16)
/* lasat 100 */
#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))

13
include/asm-mips/mach-lasat/irq.h Normal file
View File

@ -0,0 +1,13 @@
#ifndef _ASM_MACH_LASAT_IRQ_H
#define _ASM_MACH_LASAT_IRQ_H
#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 0)
#define LASAT_IRQ_BASE 8
#define LASAT_IRQ_END 23
#define NR_IRQS 24
#include_next <irq.h>
#endif /* _ASM_MACH_LASAT_IRQ_H */

2
include/asm-mips/timex.h
View File

@ -35,7 +35,7 @@ typedef unsigned int cycles_t;
static inline cycles_t get_cycles(void)
{
return read_c0_count();
return 0;
}
#endif /* __KERNEL__ */