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Merge branch 'devel-stable' into devel

Browse Source 
Conflicts:
	arch/arm/mach-pxa/clock.c
	arch/arm/mach-pxa/clock.h
This commit is contained in:
Russell King 2011-01-06 22:33:32 +00:00
commit 404a02cbd2
413 changed files with 23376 additions and 6825 deletions
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15
arch/arm/Kconfig
View File

@ -364,6 +364,14 @@ config ARCH_MXC
help
Support for Freescale MXC/iMX-based family of processors
config ARCH_MXS
bool "Freescale MXS-based"
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLKDEV
help
Support for Freescale MXS-based family of processors
config ARCH_STMP3XXX
bool "Freescale STMP3xxx"
select CPU_ARM926T
@ -817,6 +825,7 @@ config ARCH_U8500
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_CPUFREQ
help
Support for ST-Ericsson's Ux500 architecture
@ -923,6 +932,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/plat-mxc/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
@ -1022,8 +1033,8 @@ source arch/arm/mm/Kconfig
config IWMMXT
bool "Enable iWMMXt support"
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
default y if PXA27x || PXA3xx || ARCH_MMP
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.

3
arch/arm/Makefile
View File

@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx

1
arch/arm/configs/mx3_defconfig
View File

@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y

2
arch/arm/include/asm/hw_breakpoint.h
View File

@ -20,7 +20,7 @@ struct arch_hw_breakpoint_ctrl {
struct arch_hw_breakpoint {
u32 address;
u32 trigger;
struct perf_event *suspended_wp;
struct arch_hw_breakpoint_ctrl step_ctrl;
struct arch_hw_breakpoint_ctrl ctrl;
};

1
arch/arm/kernel/Makefile
View File

@ -54,6 +54,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
obj-$(CONFIG_IWMMXT) += iwmmxt.o
obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o

4
arch/arm/kernel/entry-armv.S
View File

@ -178,6 +178,7 @@ __dabt_svc:
@
@ set desired IRQ state, then call main handler
@
debug_entry r1
msr cpsr_c, r9
mov r2, sp
bl do_DataAbort
@ -304,6 +305,7 @@ __pabt_svc:
#else
bl CPU_PABORT_HANDLER
#endif
debug_entry r1
msr cpsr_c, r9 @ Maybe enable interrupts
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
@ -419,6 +421,7 @@ __dabt_usr:
@
@ IRQs on, then call the main handler
@
debug_entry r1
enable_irq
mov r2, sp
adr lr, BSYM(ret_from_exception)
@ -683,6 +686,7 @@ __pabt_usr:
#else
bl CPU_PABORT_HANDLER
#endif
debug_entry r1
enable_irq @ Enable interrupts
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler

19
arch/arm/kernel/entry-header.S
View File

@ -165,6 +165,25 @@
.endm
#endif /* !CONFIG_THUMB2_KERNEL */
@
@ Debug exceptions are taken as prefetch or data aborts.
@ We must disable preemption during the handler so that
@ we can access the debug registers safely.
@
.macro debug_entry, fsr
#if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT)
ldr r4, =0x40f @ mask out fsr.fs
and r5, r4, \fsr
cmp r5, #2 @ debug exception
bne 1f
get_thread_info r10
ldr r6, [r10, #TI_PREEMPT] @ get preempt count
add r11, r6, #1 @ increment it
str r11, [r10, #TI_PREEMPT]
1:
#endif
.endm
/*
* These are the registers used in the syscall handler, and allow us to
* have in theory up to 7 arguments to a function - r0 to r6.

531
arch/arm/kernel/hw_breakpoint.c
View File

@ -24,6 +24,7 @@
#define pr_fmt(fmt) "hw-breakpoint: " fmt
#include <linux/errno.h>
#include <linux/hardirq.h>
#include <linux/perf_event.h>
#include <linux/hw_breakpoint.h>
#include <linux/smp.h>
@ -44,6 +45,7 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
/* Number of BRP/WRP registers on this CPU. */
static int core_num_brps;
static int core_num_reserved_brps;
static int core_num_wrps;
/* Debug architecture version. */
@ -52,87 +54,6 @@ static u8 debug_arch;
/* Maximum supported watchpoint length. */
static u8 max_watchpoint_len;
/* Determine number of BRP registers available. */
static int get_num_brps(void)
{
u32 didr;
ARM_DBG_READ(c0, 0, didr);
return ((didr >> 24) & 0xf) + 1;
}
/* Determine number of WRP registers available. */
static int get_num_wrps(void)
{
/*
* FIXME: When a watchpoint fires, the only way to work out which
* watchpoint it was is by disassembling the faulting instruction
* and working out the address of the memory access.
*
* Furthermore, we can only do this if the watchpoint was precise
* since imprecise watchpoints prevent us from calculating register
* based addresses.
*
* For the time being, we only report 1 watchpoint register so we
* always know which watchpoint fired. In the future we can either
* add a disassembler and address generation emulator, or we can
* insert a check to see if the DFAR is set on watchpoint exception
* entry [the ARM ARM states that the DFAR is UNKNOWN, but
* experience shows that it is set on some implementations].
*/
#if 0
u32 didr, wrps;
ARM_DBG_READ(c0, 0, didr);
return ((didr >> 28) & 0xf) + 1;
#endif
return 1;
}
int hw_breakpoint_slots(int type)
{
/*
* We can be called early, so don't rely on
* our static variables being initialised.
*/
switch (type) {
case TYPE_INST:
return get_num_brps();
case TYPE_DATA:
return get_num_wrps();
default:
pr_warning("unknown slot type: %d\n", type);
return 0;
}
}
/* Determine debug architecture. */
static u8 get_debug_arch(void)
{
u32 didr;
/* Do we implement the extended CPUID interface? */
if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
pr_warning("CPUID feature registers not supported. "
"Assuming v6 debug is present.\n");
return ARM_DEBUG_ARCH_V6;
}
ARM_DBG_READ(c0, 0, didr);
return (didr >> 16) & 0xf;
}
/* Does this core support mismatch breakpoints? */
static int core_has_mismatch_bps(void)
{
return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1;
}
u8 arch_get_debug_arch(void)
{
return debug_arch;
}
#define READ_WB_REG_CASE(OP2, M, VAL) \
case ((OP2 << 4) + M): \
ARM_DBG_READ(c ## M, OP2, VAL); \
@ -210,6 +131,94 @@ static void write_wb_reg(int n, u32 val)
isb();
}
/* Determine debug architecture. */
static u8 get_debug_arch(void)
{
u32 didr;
/* Do we implement the extended CPUID interface? */
if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
pr_warning("CPUID feature registers not supported. "
"Assuming v6 debug is present.\n");
return ARM_DEBUG_ARCH_V6;
}
ARM_DBG_READ(c0, 0, didr);
return (didr >> 16) & 0xf;
}
u8 arch_get_debug_arch(void)
{
return debug_arch;
}
/* Determine number of BRP register available. */
static int get_num_brp_resources(void)
{
u32 didr;
ARM_DBG_READ(c0, 0, didr);
return ((didr >> 24) & 0xf) + 1;
}
/* Does this core support mismatch breakpoints? */
static int core_has_mismatch_brps(void)
{
return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
get_num_brp_resources() > 1);
}
/* Determine number of usable WRPs available. */
static int get_num_wrps(void)
{
/*
* FIXME: When a watchpoint fires, the only way to work out which
* watchpoint it was is by disassembling the faulting instruction
* and working out the address of the memory access.
*
* Furthermore, we can only do this if the watchpoint was precise
* since imprecise watchpoints prevent us from calculating register
* based addresses.
*
* Providing we have more than 1 breakpoint register, we only report
* a single watchpoint register for the time being. This way, we always
* know which watchpoint fired. In the future we can either add a
* disassembler and address generation emulator, or we can insert a
* check to see if the DFAR is set on watchpoint exception entry
* [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
* that it is set on some implementations].
*/
#if 0
int wrps;
u32 didr;
ARM_DBG_READ(c0, 0, didr);
wrps = ((didr >> 28) & 0xf) + 1;
#endif
int wrps = 1;
if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
wrps = get_num_brp_resources() - 1;
return wrps;
}
/* We reserve one breakpoint for each watchpoint. */
static int get_num_reserved_brps(void)
{
if (core_has_mismatch_brps())
return get_num_wrps();
return 0;
}
/* Determine number of usable BRPs available. */
static int get_num_brps(void)
{
int brps = get_num_brp_resources();
if (core_has_mismatch_brps())
brps -= get_num_reserved_brps();
return brps;
}
/*
* In order to access the breakpoint/watchpoint control registers,
* we must be running in debug monitor mode. Unfortunately, we can
@ -230,8 +239,12 @@ static int enable_monitor_mode(void)
goto out;
}
/* If monitor mode is already enabled, just return. */
if (dscr & ARM_DSCR_MDBGEN)
goto out;
/* Write to the corresponding DSCR. */
switch (debug_arch) {
switch (get_debug_arch()) {
case ARM_DEBUG_ARCH_V6:
case ARM_DEBUG_ARCH_V6_1:
ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
@ -246,15 +259,30 @@ static int enable_monitor_mode(void)
/* Check that the write made it through. */
ARM_DBG_READ(c1, 0, dscr);
if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
"failed to enable monitor mode.")) {
if (!(dscr & ARM_DSCR_MDBGEN))
ret = -EPERM;
}
out:
return ret;
}
int hw_breakpoint_slots(int type)
{
/*
* We can be called early, so don't rely on
* our static variables being initialised.
*/
switch (type) {
case TYPE_INST:
return get_num_brps();
case TYPE_DATA:
return get_num_wrps();
default:
pr_warning("unknown slot type: %d\n", type);
return 0;
}
}
/*
* Check if 8-bit byte-address select is available.
* This clobbers WRP 0.
@ -268,9 +296,6 @@ static u8 get_max_wp_len(void)
if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
goto out;
if (enable_monitor_mode())
goto out;
memset(&ctrl, 0, sizeof(ctrl));
ctrl.len = ARM_BREAKPOINT_LEN_8;
ctrl_reg = encode_ctrl_reg(ctrl);
@ -289,23 +314,6 @@ u8 arch_get_max_wp_len(void)
return max_watchpoint_len;
}
/*
* Handler for reactivating a suspended watchpoint when the single
* step `mismatch' breakpoint is triggered.
*/
static void wp_single_step_handler(struct perf_event *bp, int unused,
struct perf_sample_data *data,
struct pt_regs *regs)
{
perf_event_enable(counter_arch_bp(bp)->suspended_wp);
unregister_hw_breakpoint(bp);
}
static int bp_is_single_step(struct perf_event *bp)
{
return bp->overflow_handler == wp_single_step_handler;
}
/*
* Install a perf counter breakpoint.
*/
@ -314,30 +322,41 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
struct perf_event **slot, **slots;
int i, max_slots, ctrl_base, val_base, ret = 0;
u32 addr, ctrl;
/* Ensure that we are in monitor mode and halting mode is disabled. */
ret = enable_monitor_mode();
if (ret)
goto out;
addr = info->address;
ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
/* Breakpoint */
ctrl_base = ARM_BASE_BCR;
val_base = ARM_BASE_BVR;
slots = __get_cpu_var(bp_on_reg);
max_slots = core_num_brps - 1;
if (bp_is_single_step(bp)) {
info->ctrl.mismatch = 1;
i = max_slots;
slots[i] = bp;
goto setup;
slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
max_slots = core_num_brps;
if (info->step_ctrl.enabled) {
/* Override the breakpoint data with the step data. */
addr = info->trigger & ~0x3;
ctrl = encode_ctrl_reg(info->step_ctrl);
}
} else {
/* Watchpoint */
if (info->step_ctrl.enabled) {
/* Install into the reserved breakpoint region. */
ctrl_base = ARM_BASE_BCR + core_num_brps;
val_base = ARM_BASE_BVR + core_num_brps;
/* Override the watchpoint data with the step data. */
addr = info->trigger & ~0x3;
ctrl = encode_ctrl_reg(info->step_ctrl);
} else {
ctrl_base = ARM_BASE_WCR;
val_base = ARM_BASE_WVR;
slots = __get_cpu_var(wp_on_reg);
}
slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
max_slots = core_num_wrps;
}
@ -355,12 +374,11 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
goto out;
}
setup:
/* Setup the address register. */
write_wb_reg(val_base + i, info->address);
write_wb_reg(val_base + i, addr);
/* Setup the control register. */
write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
write_wb_reg(ctrl_base + i, ctrl);
out:
return ret;
@ -375,18 +393,15 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
/* Breakpoint */
base = ARM_BASE_BCR;
slots = __get_cpu_var(bp_on_reg);
max_slots = core_num_brps - 1;
if (bp_is_single_step(bp)) {
i = max_slots;
slots[i] = NULL;
goto reset;
}
slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
max_slots = core_num_brps;
} else {
/* Watchpoint */
if (info->step_ctrl.enabled)
base = ARM_BASE_BCR + core_num_brps;
else
base = ARM_BASE_WCR;
slots = __get_cpu_var(wp_on_reg);
slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
max_slots = core_num_wrps;
}
@ -403,7 +418,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
return;
reset:
/* Reset the control register. */
write_wb_reg(base + i, 0);
}
@ -537,12 +551,23 @@ static int arch_build_bp_info(struct perf_event *bp)
return -EINVAL;
}
/*
* Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
* Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
* by the hardware and must be aligned to the appropriate number of
* bytes.
*/
if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
info->ctrl.len != ARM_BREAKPOINT_LEN_4)
return -EINVAL;
/* Address */
info->address = bp->attr.bp_addr;
/* Privilege */
info->ctrl.privilege = ARM_BREAKPOINT_USER;
if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
if (arch_check_bp_in_kernelspace(bp))
info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
/* Enabled? */
@ -561,7 +586,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
int ret = 0;
u32 bytelen, max_len, offset, alignment_mask = 0x3;
u32 offset, alignment_mask = 0x3;
/* Build the arch_hw_breakpoint. */
ret = arch_build_bp_info(bp);
@ -571,84 +596,85 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
/* Check address alignment. */
if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
alignment_mask = 0x7;
if (info->address & alignment_mask) {
/*
* Try to fix the alignment. This may result in a length
* that is too large, so we must check for that.
*/
bytelen = get_hbp_len(info->ctrl.len);
max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 :
max_watchpoint_len;
if (max_len >= 8)
offset = info->address & 0x7;
else
offset = info->address & 0x3;
if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) {
ret = -EFBIG;
offset = info->address & alignment_mask;
switch (offset) {
case 0:
/* Aligned */
break;
case 1:
/* Allow single byte watchpoint. */
if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
break;
case 2:
/* Allow halfword watchpoints and breakpoints. */
if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
break;
default:
ret = -EINVAL;
goto out;
}
info->address &= ~alignment_mask;
info->ctrl.len <<= offset;
info->address &= ~offset;
pr_debug("breakpoint alignment fixup: length = 0x%x, "
"address = 0x%x\n", info->ctrl.len, info->address);
}
/*
* Currently we rely on an overflow handler to take
* care of single-stepping the breakpoint when it fires.
* In the case of userspace breakpoints on a core with V7 debug,
* we can use the mismatch feature as a poor-man's hardware single-step.
* we can use the mismatch feature as a poor-man's hardware
* single-step, but this only works for per-task breakpoints.
*/
if (WARN_ONCE(!bp->overflow_handler &&
(arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()),
(arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()
|| !bp->hw.bp_target),
"overflow handler required but none found")) {
ret = -EINVAL;
goto out;
}
out:
return ret;
}
static void update_mismatch_flag(int idx, int flag)
/*
* Enable/disable single-stepping over the breakpoint bp at address addr.
*/
static void enable_single_step(struct perf_event *bp, u32 addr)
{
struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
struct arch_hw_breakpoint *info;
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
if (bp == NULL)
return;
arch_uninstall_hw_breakpoint(bp);
info->step_ctrl.mismatch = 1;
info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
info->step_ctrl.privilege = info->ctrl.privilege;
info->step_ctrl.enabled = 1;
info->trigger = addr;
arch_install_hw_breakpoint(bp);
}
info = counter_arch_bp(bp);
/* Update the mismatch field to enter/exit `single-step' mode */
if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
info->ctrl.mismatch = flag;
write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
}
static void disable_single_step(struct perf_event *bp)
{
arch_uninstall_hw_breakpoint(bp);
counter_arch_bp(bp)->step_ctrl.enabled = 0;
arch_install_hw_breakpoint(bp);
}
static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
{
int i;
struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
struct perf_event *wp, **slots;
struct arch_hw_breakpoint *info;
struct perf_event_attr attr;
slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
/* Without a disassembler, we can only handle 1 watchpoint. */
BUG_ON(core_num_wrps > 1);
hw_breakpoint_init(&attr);
attr.bp_addr = regs->ARM_pc & ~0x3;
attr.bp_len = HW_BREAKPOINT_LEN_4;
attr.bp_type = HW_BREAKPOINT_X;
for (i = 0; i < core_num_wrps; ++i) {
rcu_read_lock();
if (slots[i] == NULL) {
wp = slots[i];
if (wp == NULL) {
rcu_read_unlock();
continue;
}
@ -658,87 +684,121 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
* single watchpoint, we can set the trigger to the lowest
* possible faulting address.
*/
info = counter_arch_bp(slots[i]);
info->trigger = slots[i]->attr.bp_addr;
info = counter_arch_bp(wp);
info->trigger = wp->attr.bp_addr;
pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
perf_bp_event(slots[i], regs);
perf_bp_event(wp, regs);
/*
* If no overflow handler is present, insert a temporary
* mismatch breakpoint so we can single-step over the
* watchpoint trigger.
*/
if (!slots[i]->overflow_handler) {
bp = register_user_hw_breakpoint(&attr,
wp_single_step_handler,
current);
counter_arch_bp(bp)->suspended_wp = slots[i];
perf_event_disable(slots[i]);
}
if (!wp->overflow_handler)
enable_single_step(wp, instruction_pointer(regs));
rcu_read_unlock();
}
}
static void watchpoint_single_step_handler(unsigned long pc)
{
int i;
struct perf_event *wp, **slots;
struct arch_hw_breakpoint *info;
slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
for (i = 0; i < core_num_reserved_brps; ++i) {
rcu_read_lock();
wp = slots[i];
if (wp == NULL)
goto unlock;
info = counter_arch_bp(wp);
if (!info->step_ctrl.enabled)
goto unlock;
/*
* Restore the original watchpoint if we've completed the
* single-step.
*/
if (info->trigger != pc)
disable_single_step(wp);
unlock:
rcu_read_unlock();
}
}
static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
{
int i;
int mismatch;
u32 ctrl_reg, val, addr;
struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
struct perf_event *bp, **slots;
struct arch_hw_breakpoint *info;
struct arch_hw_breakpoint_ctrl ctrl;
slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
/* The exception entry code places the amended lr in the PC. */
addr = regs->ARM_pc;
/* Check the currently installed breakpoints first. */
for (i = 0; i < core_num_brps; ++i) {
rcu_read_lock();
bp = slots[i];
if (bp == NULL) {
rcu_read_unlock();
continue;
}
if (bp == NULL)
goto unlock;
mismatch = 0;
info = counter_arch_bp(bp);
/* Check if the breakpoint value matches. */
val = read_wb_reg(ARM_BASE_BVR + i);
if (val != (addr & ~0x3))
goto unlock;
goto mismatch;
/* Possible match, check the byte address select to confirm. */
ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
decode_ctrl_reg(ctrl_reg, &ctrl);
if ((1 << (addr & 0x3)) & ctrl.len) {
mismatch = 1;
info = counter_arch_bp(bp);
info->trigger = addr;
}
unlock:
if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
pr_debug("breakpoint fired: address = 0x%x\n", addr);
perf_bp_event(bp, regs);
if (!bp->overflow_handler)
enable_single_step(bp, addr);
goto unlock;
}
update_mismatch_flag(i, mismatch);
mismatch:
/* If we're stepping a breakpoint, it can now be restored. */
if (info->step_ctrl.enabled)
disable_single_step(bp);
unlock:
rcu_read_unlock();
}
/* Handle any pending watchpoint single-step breakpoints. */
watchpoint_single_step_handler(addr);
}
/*
* Called from either the Data Abort Handler [watchpoint] or the
* Prefetch Abort Handler [breakpoint].
* Prefetch Abort Handler [breakpoint] with preemption disabled.
*/
static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{
int ret = 1; /* Unhandled fault. */
int ret = 0;
u32 dscr;
/* We must be called with preemption disabled. */
WARN_ON(preemptible());
/* We only handle watchpoints and hardware breakpoints. */
ARM_DBG_READ(c1, 0, dscr);
@ -753,25 +813,47 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
watchpoint_handler(addr, regs);
break;
default:
goto out;
ret = 1; /* Unhandled fault. */
}
ret = 0;
out:
/*
* Re-enable preemption after it was disabled in the
* low-level exception handling code.
*/
preempt_enable();
return ret;
}
/*
* One-time initialisation.
*/
static void __init reset_ctrl_regs(void *unused)
static void reset_ctrl_regs(void *unused)
{
int i;
/*
* v7 debug contains save and restore registers so that debug state
* can be maintained across low-power modes without leaving
* the debug logic powered up. It is IMPLEMENTATION DEFINED whether
* we can write to the debug registers out of reset, so we must
* unlock the OS Lock Access Register to avoid taking undefined
* instruction exceptions later on.
*/
if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
/*
* Unconditionally clear the lock by writing a value
* other than 0xC5ACCE55 to the access register.
*/
asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
isb();
}
if (enable_monitor_mode())
return;
for (i = 0; i < core_num_brps; ++i) {
/* We must also reset any reserved registers. */
for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
write_wb_reg(ARM_BASE_BCR + i, 0UL);
write_wb_reg(ARM_BASE_BVR + i, 0UL);
}
@ -782,45 +864,57 @@ static void __init reset_ctrl_regs(void *unused)
}
}
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
if (action == CPU_ONLINE)
smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata dbg_reset_nb = {
.notifier_call = dbg_reset_notify,
};
static int __init arch_hw_breakpoint_init(void)
{
int ret = 0;
u32 dscr;
debug_arch = get_debug_arch();
if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
ret = -ENODEV;
goto out;
return 0;
}
/* Determine how many BRPs/WRPs are available. */
core_num_brps = get_num_brps();
core_num_reserved_brps = get_num_reserved_brps();
core_num_wrps = get_num_wrps();
pr_info("found %d breakpoint and %d watchpoint registers.\n",
core_num_brps, core_num_wrps);
core_num_brps + core_num_reserved_brps, core_num_wrps);
if (core_has_mismatch_bps())
pr_info("1 breakpoint reserved for watchpoint single-step.\n");
if (core_num_reserved_brps)
pr_info("%d breakpoint(s) reserved for watchpoint "
"single-step.\n", core_num_reserved_brps);
ARM_DBG_READ(c1, 0, dscr);
if (dscr & ARM_DSCR_HDBGEN) {
pr_warning("halting debug mode enabled. Assuming maximum "
"watchpoint size of 4 bytes.");
} else {
/* Work out the maximum supported watchpoint length. */
max_watchpoint_len = get_max_wp_len();
pr_info("maximum watchpoint size is %u bytes.\n",
max_watchpoint_len);
/*
* Reset the breakpoint resources. We assume that a halting
* debugger will leave the world in a nice state for us.
*/
smp_call_function(reset_ctrl_regs, NULL, 1);
reset_ctrl_regs(NULL);
/* Work out the maximum supported watchpoint length. */
max_watchpoint_len = get_max_wp_len();
pr_info("maximum watchpoint size is %u bytes.\n",
max_watchpoint_len);
}
/* Register debug fault handler. */
@ -829,8 +923,9 @@ static int __init arch_hw_breakpoint_init(void)
hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
"breakpoint debug exception");
out:
return ret;
/* Register hotplug notifier. */
register_cpu_notifier(&dbg_reset_nb);
return 0;
}
arch_initcall(arch_hw_breakpoint_init);

55
arch/arm/kernel/iwmmxt.S
View File

@ -19,6 +19,14 @@
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#if defined(CONFIG_CPU_PJ4)
#define PJ4(code...) code
#define XSC(code...)
#else
#define PJ4(code...)
#define XSC(code...) code
#endif
#define MMX_WR0 (0x00)
#define MMX_WR1 (0x08)
#define MMX_WR2 (0x10)
@ -58,11 +66,17 @@
ENTRY(iwmmxt_task_enable)
mrc p15, 0, r2, c15, c1, 0
tst r2, #0x3 @ CP0 and CP1 accessible?
XSC(mrc p15, 0, r2, c15, c1, 0)
PJ4(mrc p15, 0, r2, c1, c0, 2)
@ CP0 and CP1 accessible?
XSC(tst r2, #0x3)
PJ4(tst r2, #0xf)
movne pc, lr @ if so no business here
orr r2, r2, #0x3 @ enable access to CP0 and CP1
mcr p15, 0, r2, c15, c1, 0
@ enable access to CP0 and CP1
XSC(orr r2, r2, #0x3)
XSC(mcr p15, 0, r2, c15, c1, 0)
PJ4(orr r2, r2, #0xf)
PJ4(mcr p15, 0, r2, c1, c0, 2)
ldr r3, =concan_owner
add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable)
teqne r1, r2 @ or specified one?
bne 1f @ no: quit
mrc p15, 0, r4, c15, c1, 0
orr r4, r4, #0x3 @ enable access to CP0 and CP1
mcr p15, 0, r4, c15, c1, 0
@ enable access to CP0 and CP1
XSC(mrc p15, 0, r4, c15, c1, 0)
XSC(orr r4, r4, #0xf)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(mrc p15, 0, r4, c1, c0, 2)
PJ4(orr r4, r4, #0x3)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mov r0, #0 @ nothing to load
str r0, [r3] @ no more current owner
mrc p15, 0, r2, c2, c0, 0
mov r2, r2 @ cpwait
bl concan_save
bic r4, r4, #0x3 @ disable access to CP0 and CP1
mcr p15, 0, r4, c15, c1, 0
@ disable access to CP0 and CP1
XSC(bic r4, r4, #0x3)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(bic r4, r4, #0xf)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mrc p15, 0, r2, c2, c0, 0
mov r2, r2 @ cpwait
@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore)
*/
ENTRY(iwmmxt_task_switch)
mrc p15, 0, r1, c15, c1, 0
tst r1, #0x3 @ CP0 and CP1 accessible?
XSC(mrc p15, 0, r1, c15, c1, 0)
PJ4(mrc p15, 0, r1, c1, c0, 2)
@ CP0 and CP1 accessible?
XSC(tst r1, #0x3)
PJ4(tst r1, #0xf)
bne 1f @ yes: block them for next task
ldr r2, =concan_owner
@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch)
teq r2, r3 @ next task owns it?
movne pc, lr @ no: leave Concan disabled
1: eor r1, r1, #3 @ flip Concan access
mcr p15, 0, r1, c15, c1, 0
1: @ flip Conan access
XSC(eor r1, r1, #0x3)
XSC(mcr p15, 0, r1, c15, c1, 0)
PJ4(eor r1, r1, #0xf)
PJ4(mcr p15, 0, r1, c1, c0, 2)
mrc p15, 0, r1, c2, c0, 0
sub pc, lr, r1, lsr #32 @ cpwait and return

14
arch/arm/kernel/perf_event.c
View File

@ -32,7 +32,7 @@ static struct platform_device *pmu_device;
* Hardware lock to serialize accesses to PMU registers. Needed for the
* read/modify/write sequences.
*/
DEFINE_SPINLOCK(pmu_lock);
static DEFINE_RAW_SPINLOCK(pmu_lock);
/*
* ARMv6 supports a maximum of 3 events, starting from index 1. If we add
@ -65,7 +65,7 @@ struct cpu_hw_events {
*/
unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
};
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
struct arm_pmu {
enum arm_perf_pmu_ids id;
@ -673,7 +673,7 @@ arch_initcall(init_hw_perf_events);
* This code has been adapted from the ARM OProfile support.
*/
struct frame_tail {
struct frame_tail *fp;
struct frame_tail __user *fp;
unsigned long sp;
unsigned long lr;
} __attribute__((packed));
@ -682,8 +682,8 @@ struct frame_tail {
* Get the return address for a single stackframe and return a pointer to the
* next frame tail.
*/
static struct frame_tail *
user_backtrace(struct frame_tail *tail,
static struct frame_tail __user *
user_backtrace(struct frame_tail __user *tail,
struct perf_callchain_entry *entry)
{
struct frame_tail buftail;
@ -709,10 +709,10 @@ user_backtrace(struct frame_tail *tail,
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
{
struct frame_tail *tail;
struct frame_tail __user *tail;
tail = (struct frame_tail *)regs->ARM_fp - 1;
tail = (struct frame_tail __user *)regs->ARM_fp - 1;
while (tail && !((unsigned long)tail & 0x3))
tail = user_backtrace(tail, entry);

30
arch/arm/kernel/perf_event_v6.c
View File

@ -400,7 +400,7 @@ armv6pmu_write_counter(int counter,
WARN_ONCE(1, "invalid counter number (%d)\n", counter);
}
void
static void
armv6pmu_enable_event(struct hw_perf_event *hwc,
int idx)
{
@ -426,12 +426,12 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
* Mask out the current event and set the counter to count the event
* that we're interested in.
*/
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = armv6_pmcr_read();
val &= ~mask;
val |= evt;
armv6_pmcr_write(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static irqreturn_t
@ -500,11 +500,11 @@ armv6pmu_start(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = armv6_pmcr_read();
val |= ARMV6_PMCR_ENABLE;
armv6_pmcr_write(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -512,11 +512,11 @@ armv6pmu_stop(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = armv6_pmcr_read();
val &= ~ARMV6_PMCR_ENABLE;
armv6_pmcr_write(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static int
@ -570,12 +570,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
* of ETM bus signal assertion cycles. The external reporting should
* be disabled and so this should never increment.
*/
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = armv6_pmcr_read();
val &= ~mask;
val |= evt;
armv6_pmcr_write(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -599,12 +599,12 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
* Unlike UP ARMv6, we don't have a way of stopping the counters. We
* simply disable the interrupt reporting.
*/
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = armv6_pmcr_read();
val &= ~mask;
val |= evt;
armv6_pmcr_write(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static const struct arm_pmu armv6pmu = {
@ -625,7 +625,7 @@ static const struct arm_pmu armv6pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init armv6pmu_init(void)
static const struct arm_pmu *__init armv6pmu_init(void)
{
return &armv6pmu;
}
@ -655,17 +655,17 @@ static const struct arm_pmu armv6mpcore_pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init armv6mpcore_pmu_init(void)
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
{
return &armv6mpcore_pmu;
}
#else
const struct arm_pmu *__init armv6pmu_init(void)
static const struct arm_pmu *__init armv6pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init armv6mpcore_pmu_init(void)
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
{
return NULL;
}

26
arch/arm/kernel/perf_event_v7.c
View File

@ -681,7 +681,7 @@ static void armv7_pmnc_dump_regs(void)
}
#endif
void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
{
unsigned long flags;
@ -689,7 +689,7 @@ void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
* Enable counter and interrupt, and set the counter to count
* the event that we're interested in.
*/
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
/*
* Disable counter
@ -713,7 +713,7 @@ void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
*/
armv7_pmnc_enable_counter(idx);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
@ -723,7 +723,7 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
/*
* Disable counter and interrupt
*/
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
/*
* Disable counter
@ -735,7 +735,7 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
*/
armv7_pmnc_disable_intens(idx);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
@ -805,20 +805,20 @@ static void armv7pmu_start(void)
{
unsigned long flags;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
/* Enable all counters */
armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void armv7pmu_stop(void)
{
unsigned long flags;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
/* Disable all counters */
armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
@ -874,7 +874,7 @@ static u32 __init armv7_reset_read_pmnc(void)
return nb_cnt + 1;
}
const struct arm_pmu *__init armv7_a8_pmu_init(void)
static const struct arm_pmu *__init armv7_a8_pmu_init(void)
{
armv7pmu.id = ARM_PERF_PMU_ID_CA8;
armv7pmu.name = "ARMv7 Cortex-A8";
@ -884,7 +884,7 @@ const struct arm_pmu *__init armv7_a8_pmu_init(void)
return &armv7pmu;
}
const struct arm_pmu *__init armv7_a9_pmu_init(void)
static const struct arm_pmu *__init armv7_a9_pmu_init(void)
{
armv7pmu.id = ARM_PERF_PMU_ID_CA9;
armv7pmu.name = "ARMv7 Cortex-A9";
@ -894,12 +894,12 @@ const struct arm_pmu *__init armv7_a9_pmu_init(void)
return &armv7pmu;
}
#else
const struct arm_pmu *__init armv7_a8_pmu_init(void)
static const struct arm_pmu *__init armv7_a8_pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init armv7_a9_pmu_init(void)
static const struct arm_pmu *__init armv7_a9_pmu_init(void)
{
return NULL;
}

40
arch/arm/kernel/perf_event_xscale.c
View File

@ -291,12 +291,12 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
return;
}
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale1pmu_read_pmnc();
val &= ~mask;
val |= evt;
xscale1pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -322,12 +322,12 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
return;
}
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale1pmu_read_pmnc();
val &= ~mask;
val |= evt;
xscale1pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static int
@ -355,11 +355,11 @@ xscale1pmu_start(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale1pmu_read_pmnc();
val |= XSCALE_PMU_ENABLE;
xscale1pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -367,11 +367,11 @@ xscale1pmu_stop(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale1pmu_read_pmnc();
val &= ~XSCALE_PMU_ENABLE;
xscale1pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static inline u32
@ -428,7 +428,7 @@ static const struct arm_pmu xscale1pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init xscale1pmu_init(void)
static const struct arm_pmu *__init xscale1pmu_init(void)
{
return &xscale1pmu;
}
@ -635,10 +635,10 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
return;
}
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
xscale2pmu_write_event_select(evtsel);
xscale2pmu_write_int_enable(ien);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -678,10 +678,10 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
return;
}
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
xscale2pmu_write_event_select(evtsel);
xscale2pmu_write_int_enable(ien);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static int
@ -705,11 +705,11 @@ xscale2pmu_start(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
val |= XSCALE_PMU_ENABLE;
xscale2pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static void
@ -717,11 +717,11 @@ xscale2pmu_stop(void)
{
unsigned long flags, val;
spin_lock_irqsave(&pmu_lock, flags);
raw_spin_lock_irqsave(&pmu_lock, flags);
val = xscale2pmu_read_pmnc();
val &= ~XSCALE_PMU_ENABLE;
xscale2pmu_write_pmnc(val);
spin_unlock_irqrestore(&pmu_lock, flags);
raw_spin_unlock_irqrestore(&pmu_lock, flags);
}
static inline u32
@ -790,17 +790,17 @@ static const struct arm_pmu xscale2pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init xscale2pmu_init(void)
static const struct arm_pmu *__init xscale2pmu_init(void)
{
return &xscale2pmu;
}
#else
const struct arm_pmu *__init xscale1pmu_init(void)
static const struct arm_pmu *__init xscale1pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init xscale2pmu_init(void)
static const struct arm_pmu *__init xscale2pmu_init(void)
{
return NULL;
}

94
arch/arm/kernel/pj4-cp0.c Normal file
View File

@ -0,0 +1,94 @@
/*
* linux/arch/arm/kernel/pj4-cp0.c
*
* PJ4 iWMMXt coprocessor context switching and handling
*
* Copyright (c) 2010 Marvell International Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/thread_notify.h>
static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
{
struct thread_info *thread = t;
switch (cmd) {
case THREAD_NOTIFY_FLUSH:
/*
* flush_thread() zeroes thread->fpstate, so no need
* to do anything here.
*
* FALLTHROUGH: Ensure we don't try to overwrite our newly
* initialised state information on the first fault.
*/
case THREAD_NOTIFY_EXIT:
iwmmxt_task_release(thread);
break;
case THREAD_NOTIFY_SWITCH:
iwmmxt_task_switch(thread);
break;
}
return NOTIFY_DONE;
}
static struct notifier_block iwmmxt_notifier_block = {
.notifier_call = iwmmxt_do,
};
static u32 __init pj4_cp_access_read(void)
{
u32 value;
__asm__ __volatile__ (
"mrc p15, 0, %0, c1, c0, 2\n\t"
: "=r" (value));
return value;
}
static void __init pj4_cp_access_write(u32 value)
{
u32 temp;
__asm__ __volatile__ (
"mcr p15, 0, %1, c1, c0, 2\n\t"
"mrc p15, 0, %0, c1, c0, 2\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) : "r" (value));
}
/*
* Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
* switch code handle iWMMXt context switching.
*/
static int __init pj4_cp0_init(void)
{
u32 cp_access;
cp_access = pj4_cp_access_read() & ~0xf;
pj4_cp_access_write(cp_access);
printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
elf_hwcap |= HWCAP_IWMMXT;
thread_register_notifier(&iwmmxt_notifier_block);
return 0;
}
late_initcall(pj4_cp0_init);

54
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@ -17,6 +17,7 @@
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
@ -107,11 +108,64 @@ static void __init cns3420_early_serial_setup(void)
#endif
}
/*
* USB
*/
static struct resource cns3xxx_usb_ehci_resources[] = {
[0] = {
.start = CNS3XXX_USB_BASE,
.end = CNS3XXX_USB_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CNS3XXX_USB_EHCI,
.flags = IORESOURCE_IRQ,
},
};
static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
static struct platform_device cns3xxx_usb_ehci_device = {
.name = "cns3xxx-ehci",
.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
.resource = cns3xxx_usb_ehci_resources,
.dev = {
.dma_mask = &cns3xxx_usb_ehci_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource cns3xxx_usb_ohci_resources[] = {
[0] = {
.start = CNS3XXX_USB_OHCI_BASE,
.end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CNS3XXX_USB_OHCI,
.flags = IORESOURCE_IRQ,
},
};
static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
static struct platform_device cns3xxx_usb_ohci_device = {
.name = "cns3xxx-ohci",
.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
.resource = cns3xxx_usb_ohci_resources,
.dev = {
.dma_mask = &cns3xxx_usb_ohci_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/*
* Initialization
*/
static struct platform_device *cns3420_pdevs[] __initdata = {
&cns3420_nor_pdev,
&cns3xxx_usb_ehci_device,
&cns3xxx_usb_ohci_device,
};
static void __init cns3420_init(void)

2
arch/arm/mach-cns3xxx/core.h
View File

@ -16,7 +16,5 @@ extern struct sys_timer cns3xxx_timer;
void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);
void cns3xxx_pwr_power_up(unsigned int block);
void cns3xxx_pwr_power_down(unsigned int block);
#endif /* __CNS3XXX_CORE_H */

1
arch/arm/mach-cns3xxx/devices.c
View File

@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "core.h"
#include "devices.h"

2
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
View File

@ -165,7 +165,6 @@
#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
#define CNS3XXX_SATA2_SIZE SZ_16M
@ -184,7 +183,6 @@
#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000

23
arch/arm/mach-cns3xxx/include/mach/pm.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright 2000 Deep Blue Solutions Ltd
* Copyright 2004 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __CNS3XXX_PM_H
#define __CNS3XXX_PM_H
#include <asm/atomic.h>
void cns3xxx_pwr_clk_en(unsigned int block);
void cns3xxx_pwr_clk_dis(unsigned int block);
void cns3xxx_pwr_power_up(unsigned int block);
void cns3xxx_pwr_power_down(unsigned int block);
extern atomic_t usb_pwr_ref;
#endif /* __CNS3XXX_PM_H */

23
arch/arm/mach-cns3xxx/pm.c
View File

@ -6,10 +6,14 @@
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/atomic.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>
void cns3xxx_pwr_clk_en(unsigned int block)
{
@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block)
reg |= (block & PM_CLK_GATE_REG_MASK);
__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
void cns3xxx_pwr_clk_dis(unsigned int block)
{
u32 reg = __raw_readl(PM_CLK_GATE_REG);
reg &= ~(block & PM_CLK_GATE_REG_MASK);
__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
void cns3xxx_pwr_power_up(unsigned int block)
{
@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block)
/* Wait for 300us for the PLL output clock locked. */
udelay(300);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_up);
void cns3xxx_pwr_power_down(unsigned int block)
{
@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block)
reg |= (block & CNS3XXX_PWR_PLL_ALL);
__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_down);
static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
reg &= ~(block & PM_SOFT_RST_REG_MASK);
} else {
reg &= ~(block & PM_SOFT_RST_REG_MASK);
__raw_writel(reg, PM_SOFT_RST_REG);
reg |= (block & PM_SOFT_RST_REG_MASK);
}
__raw_writel(reg, PM_SOFT_RST_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
void cns3xxx_pwr_soft_rst(unsigned int block)
{
@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
}
cns3xxx_pwr_soft_rst_force(block);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
void arch_reset(char mode, const char *cmd)
{
@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void)
return cpu;
}
EXPORT_SYMBOL(cns3xxx_cpu_clock);
atomic_t usb_pwr_ref = ATOMIC_INIT(0);
EXPORT_SYMBOL(usb_pwr_ref);

19
arch/arm/mach-davinci/Kconfig
View File

@ -61,6 +61,8 @@ config MACH_DAVINCI_EVM
bool "TI DM644x EVM"
default ARCH_DAVINCI_DM644x
depends on ARCH_DAVINCI_DM644x
select MISC_DEVICES
select EEPROM_AT24
help
Configure this option to specify the whether the board used
for development is a DM644x EVM
@ -68,6 +70,8 @@ config MACH_DAVINCI_EVM
config MACH_SFFSDR
bool "Lyrtech SFFSDR"
depends on ARCH_DAVINCI_DM644x
select MISC_DEVICES
select EEPROM_AT24
help
Say Y here to select the Lyrtech Small Form Factor
Software Defined Radio (SFFSDR) board.
@ -99,6 +103,8 @@ config MACH_DAVINCI_DM6467_EVM
default ARCH_DAVINCI_DM646x
depends on ARCH_DAVINCI_DM646x
select MACH_DAVINCI_DM6467TEVM
select MISC_DEVICES
select EEPROM_AT24
help
Configure this option to specify the whether the board used
for development is a DM6467 EVM
@ -110,6 +116,8 @@ config MACH_DAVINCI_DM365_EVM
bool "TI DM365 EVM"
default ARCH_DAVINCI_DM365
depends on ARCH_DAVINCI_DM365
select MISC_DEVICES
select EEPROM_AT24
help
Configure this option to specify whether the board used
for development is a DM365 EVM
@ -119,6 +127,8 @@ config MACH_DAVINCI_DA830_EVM
default ARCH_DAVINCI_DA830
depends on ARCH_DAVINCI_DA830
select GPIO_PCF857X
select MISC_DEVICES
select EEPROM_AT24
help
Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
@ -148,7 +158,6 @@ config MACH_DAVINCI_DA850_EVM
bool "TI DA850/OMAP-L138/AM18x Reference Platform"
default ARCH_DAVINCI_DA850
depends on ARCH_DAVINCI_DA850
select GPIO_PCA953X
help
Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
@ -178,6 +187,12 @@ config DA850_UI_RMII
endchoice
config GPIO_PCA953X
default MACH_DAVINCI_DA850_EVM
config KEYBOARD_GPIO_POLLED
default MACH_DAVINCI_DA850_EVM
config MACH_TNETV107X
bool "TI TNETV107X Reference Platform"
default ARCH_DAVINCI_TNETV107X
@ -188,6 +203,8 @@ config MACH_TNETV107X
config MACH_MITYOMAPL138
bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
depends on ARCH_DAVINCI_DA850
select MISC_DEVICES
select EEPROM_AT24
help
Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
System on Module. Information on this SoM may be found at

2
arch/arm/mach-davinci/aemif.c
View File

@ -90,7 +90,7 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
void __iomem *base, unsigned cs)
{
unsigned set, val;
unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
unsigned offset = A1CR_OFFSET + cs * 4;
struct clk *aemif_clk;
unsigned long clkrate;

341
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -17,8 +17,10 @@
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/i2c/pca953x.h>
#include <linux/input.h>
#include <linux/mfd/tps6507x.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -266,34 +268,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel)
struct davinci_soc_info *soc_info = &davinci_soc_info;
soc_info->emac_pdata->rmii_en = 1;
gpio_set_value(rmii_sel, 0);
gpio_set_value_cansleep(rmii_sel, 0);
}
#else
static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
#endif
#define DA850_KEYS_DEBOUNCE_MS 10
/*
* At 200ms polling interval it is possible to miss an
* event by tapping very lightly on the push button but most
* pushes do result in an event; longer intervals require the
* user to hold the button whereas shorter intervals require
* more CPU time for polling.
*/
#define DA850_GPIO_KEYS_POLL_MS 200
enum da850_evm_ui_exp_pins {
DA850_EVM_UI_EXP_SEL_C = 5,
DA850_EVM_UI_EXP_SEL_B,
DA850_EVM_UI_EXP_SEL_A,
DA850_EVM_UI_EXP_PB8,
DA850_EVM_UI_EXP_PB7,
DA850_EVM_UI_EXP_PB6,
DA850_EVM_UI_EXP_PB5,
DA850_EVM_UI_EXP_PB4,
DA850_EVM_UI_EXP_PB3,
DA850_EVM_UI_EXP_PB2,
DA850_EVM_UI_EXP_PB1,
};
static const char const *da850_evm_ui_exp[] = {
[DA850_EVM_UI_EXP_SEL_C] = "sel_c",
[DA850_EVM_UI_EXP_SEL_B] = "sel_b",
[DA850_EVM_UI_EXP_SEL_A] = "sel_a",
[DA850_EVM_UI_EXP_PB8] = "pb8",
[DA850_EVM_UI_EXP_PB7] = "pb7",
[DA850_EVM_UI_EXP_PB6] = "pb6",
[DA850_EVM_UI_EXP_PB5] = "pb5",
[DA850_EVM_UI_EXP_PB4] = "pb4",
[DA850_EVM_UI_EXP_PB3] = "pb3",
[DA850_EVM_UI_EXP_PB2] = "pb2",
[DA850_EVM_UI_EXP_PB1] = "pb1",
};
#define DA850_N_UI_PB 8
static struct gpio_keys_button da850_evm_ui_keys[] = {
[0 ... DA850_N_UI_PB - 1] = {
.type = EV_KEY,
.active_low = 1,
.wakeup = 0,
.debounce_interval = DA850_KEYS_DEBOUNCE_MS,
.code = -1, /* assigned at runtime */
.gpio = -1, /* assigned at runtime */
.desc = NULL, /* assigned at runtime */
},
};
static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
.buttons = da850_evm_ui_keys,
.nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
.poll_interval = DA850_GPIO_KEYS_POLL_MS,
};
static struct platform_device da850_evm_ui_keys_device = {
.name = "gpio-keys-polled",
.id = 0,
.dev = {
.platform_data = &da850_evm_ui_keys_pdata
},
};
static void da850_evm_ui_keys_init(unsigned gpio)
{
int i;
struct gpio_keys_button *button;
for (i = 0; i < DA850_N_UI_PB; i++) {
button = &da850_evm_ui_keys[i];
button->code = KEY_F8 - i;
button->desc = (char *)
da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
}
}
static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
unsigned ngpio, void *c)
{
int sel_a, sel_b, sel_c, ret;
sel_a = gpio + 7;
sel_b = gpio + 6;
sel_c = gpio + 5;
sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
ret = gpio_request(sel_a, "sel_a");
ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
if (ret) {
pr_warning("Cannot open UI expander pin %d\n", sel_a);
goto exp_setup_sela_fail;
}
ret = gpio_request(sel_b, "sel_b");
ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
if (ret) {
pr_warning("Cannot open UI expander pin %d\n", sel_b);
goto exp_setup_selb_fail;
}
ret = gpio_request(sel_c, "sel_c");
ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
if (ret) {
pr_warning("Cannot open UI expander pin %d\n", sel_c);
goto exp_setup_selc_fail;
@ -304,6 +387,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
gpio_direction_output(sel_b, 1);
gpio_direction_output(sel_c, 1);
da850_evm_ui_keys_init(gpio);
ret = platform_device_register(&da850_evm_ui_keys_device);
if (ret) {
pr_warning("Could not register UI GPIO expander push-buttons");
goto exp_setup_keys_fail;
}
ui_card_detected = 1;
pr_info("DA850/OMAP-L138 EVM UI card detected\n");
@ -313,6 +403,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
return 0;
exp_setup_keys_fail:
gpio_free(sel_c);
exp_setup_selc_fail:
gpio_free(sel_b);
exp_setup_selb_fail:
@ -324,14 +416,192 @@ exp_setup_sela_fail:
static int da850_evm_ui_expander_teardown(struct i2c_client *client,
unsigned gpio, unsigned ngpio, void *c)
{
/* deselect all functionalities */
gpio_set_value(gpio + 5, 1);
gpio_set_value(gpio + 6, 1);
gpio_set_value(gpio + 7, 1);
platform_device_unregister(&da850_evm_ui_keys_device);
gpio_free(gpio + 5);
gpio_free(gpio + 6);
gpio_free(gpio + 7);
/* deselect all functionalities */
gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
return 0;
}
/* assign the baseboard expander's GPIOs after the UI board's */
#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
enum da850_evm_bb_exp_pins {
DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
DA850_EVM_BB_EXP_SW_RST,
DA850_EVM_BB_EXP_TP_23,
DA850_EVM_BB_EXP_TP_22,
DA850_EVM_BB_EXP_TP_21,
DA850_EVM_BB_EXP_USER_PB1,
DA850_EVM_BB_EXP_USER_LED2,
DA850_EVM_BB_EXP_USER_LED1,
DA850_EVM_BB_EXP_USER_SW1,
DA850_EVM_BB_EXP_USER_SW2,
DA850_EVM_BB_EXP_USER_SW3,
DA850_EVM_BB_EXP_USER_SW4,
DA850_EVM_BB_EXP_USER_SW5,
DA850_EVM_BB_EXP_USER_SW6,
DA850_EVM_BB_EXP_USER_SW7,
DA850_EVM_BB_EXP_USER_SW8
};
static const char const *da850_evm_bb_exp[] = {
[DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
[DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
[DA850_EVM_BB_EXP_TP_23] = "tp_23",
[DA850_EVM_BB_EXP_TP_22] = "tp_22",
[DA850_EVM_BB_EXP_TP_21] = "tp_21",
[DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
[DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
[DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
[DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
[DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
[DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
[DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
[DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
[DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
[DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
[DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
};
#define DA850_N_BB_USER_SW 8
static struct gpio_keys_button da850_evm_bb_keys[] = {
[0] = {
.type = EV_KEY,
.active_low = 1,
.wakeup = 0,
.debounce_interval = DA850_KEYS_DEBOUNCE_MS,
.code = KEY_PROG1,
.desc = NULL, /* assigned at runtime */
.gpio = -1, /* assigned at runtime */
},
[1 ... DA850_N_BB_USER_SW] = {
.type = EV_SW,
.active_low = 1,
.wakeup = 0,
.debounce_interval = DA850_KEYS_DEBOUNCE_MS,
.code = -1, /* assigned at runtime */
.desc = NULL, /* assigned at runtime */
.gpio = -1, /* assigned at runtime */
},
};
static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
.buttons = da850_evm_bb_keys,
.nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
.poll_interval = DA850_GPIO_KEYS_POLL_MS,
};
static struct platform_device da850_evm_bb_keys_device = {
.name = "gpio-keys-polled",
.id = 1,
.dev = {
.platform_data = &da850_evm_bb_keys_pdata
},
};
static void da850_evm_bb_keys_init(unsigned gpio)
{
int i;
struct gpio_keys_button *button;
button = &da850_evm_bb_keys[0];
button->desc = (char *)
da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
for (i = 0; i < DA850_N_BB_USER_SW; i++) {
button = &da850_evm_bb_keys[i + 1];
button->code = SW_LID + i;
button->desc = (char *)
da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
}
}
#define DA850_N_BB_USER_LED 2
static struct gpio_led da850_evm_bb_leds[] = {
[0 ... DA850_N_BB_USER_LED - 1] = {
.active_low = 1,
.gpio = -1, /* assigned at runtime */
.name = NULL, /* assigned at runtime */
},
};
static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
.leds = da850_evm_bb_leds,
.num_leds = ARRAY_SIZE(da850_evm_bb_leds),
};
static struct platform_device da850_evm_bb_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &da850_evm_bb_leds_pdata
}
};
static void da850_evm_bb_leds_init(unsigned gpio)
{
int i;
struct gpio_led *led;
for (i = 0; i < DA850_N_BB_USER_LED; i++) {
led = &da850_evm_bb_leds[i];
led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
led->name =
da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
}
}
static int da850_evm_bb_expander_setup(struct i2c_client *client,
unsigned gpio, unsigned ngpio,
void *c)
{
int ret;
/*
* Register the switches and pushbutton on the baseboard as a gpio-keys
* device.
*/
da850_evm_bb_keys_init(gpio);
ret = platform_device_register(&da850_evm_bb_keys_device);
if (ret) {
pr_warning("Could not register baseboard GPIO expander keys");
goto io_exp_setup_sw_fail;
}
da850_evm_bb_leds_init(gpio);
ret = platform_device_register(&da850_evm_bb_leds_device);
if (ret) {
pr_warning("Could not register baseboard GPIO expander LEDS");
goto io_exp_setup_leds_fail;
}
return 0;
io_exp_setup_leds_fail:
platform_device_unregister(&da850_evm_bb_keys_device);
io_exp_setup_sw_fail:
return ret;
}
static int da850_evm_bb_expander_teardown(struct i2c_client *client,
unsigned gpio, unsigned ngpio, void *c)
{
platform_device_unregister(&da850_evm_bb_leds_device);
platform_device_unregister(&da850_evm_bb_keys_device);
return 0;
}
@ -340,6 +610,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = {
.gpio_base = DAVINCI_N_GPIO,
.setup = da850_evm_ui_expander_setup,
.teardown = da850_evm_ui_expander_teardown,
.names = da850_evm_ui_exp,
};
static struct pca953x_platform_data da850_evm_bb_expander_info = {
.gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
.setup = da850_evm_bb_expander_setup,
.teardown = da850_evm_bb_expander_teardown,
.names = da850_evm_bb_exp,
};
static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
@ -350,6 +628,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
I2C_BOARD_INFO("tca6416", 0x20),
.platform_data = &da850_evm_ui_expander_info,
},
{
I2C_BOARD_INFO("tca6416", 0x21),
.platform_data = &da850_evm_bb_expander_info,
},
};
static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@ -540,7 +822,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
{
.constraints = {
.min_uV = 950000,
.max_uV = 1320000,
.max_uV = 1350000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
@ -591,7 +873,7 @@ static struct tps6507x_board tps_board = {
.tps6507x_ts_init_data = &tps6507x_touchscreen_data,
};
static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
{
I2C_BOARD_INFO("tps6507x", 0x48),
.platform_data = &tps_board,
@ -600,8 +882,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
static int __init pmic_tps65070_init(void)
{
return i2c_register_board_info(1, da850evm_tps65070_info,
ARRAY_SIZE(da850evm_tps65070_info));
return i2c_register_board_info(1, da850_evm_tps65070_info,
ARRAY_SIZE(da850_evm_tps65070_info));
}
static const short da850_evm_lcdc_pins[] = {
@ -736,6 +1018,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
&da850_edma_cc1_rsv,
};
#ifdef CONFIG_CPU_FREQ
static __init int da850_evm_init_cpufreq(void)
{
switch (system_rev & 0xF) {
case 3:
da850_max_speed = 456000;
break;
case 2:
da850_max_speed = 408000;
break;
case 1:
da850_max_speed = 372000;
break;
}
return da850_register_cpufreq("pll0_sysclk3");
}
#else
static __init int da850_evm_init_cpufreq(void) { return 0; }
#endif
static __init void da850_evm_init(void)
{
int ret;
@ -836,7 +1139,7 @@ static __init void da850_evm_init(void)
if (ret)
pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
ret = da850_register_cpufreq("pll0_sysclk3");
ret = da850_evm_init_cpufreq();
if (ret)
pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
ret);

4
arch/arm/mach-davinci/clock.c
View File

@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
ratio--;
}
if (ratio > PLLDIV_RATIO_MASK)
if (ratio > pll->div_ratio_mask)
return -EINVAL;
do {
@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
} while (v & PLLSTAT_GOSTAT);
v = __raw_readl(pll->base + clk->div_reg);
v &= ~PLLDIV_RATIO_MASK;
v &= ~pll->div_ratio_mask;
v |= ratio | PLLDIV_EN;
__raw_writel(v, pll->base + clk->div_reg);

75
arch/arm/mach-davinci/da850.c
View File

@ -830,8 +830,7 @@ static void da850_set_async3_src(int pllnum)
* According to the TRM, minimum PLLM results in maximum power savings.
* The OPP definitions below should keep the PLLM as low as possible.
*
* The output of the PLLM must be between 400 to 600 MHz.
* This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
* The output of the PLLM must be between 300 to 600 MHz.
*/
struct da850_opp {
unsigned int freq; /* in KHz */
@ -842,6 +841,33 @@ struct da850_opp {
unsigned int cvdd_max; /* in uV */
};
static const struct da850_opp da850_opp_456 = {
.freq = 456000,
.prediv = 1,
.mult = 19,
.postdiv = 1,
.cvdd_min = 1300000,
.cvdd_max = 1350000,
};
static const struct da850_opp da850_opp_408 = {
.freq = 408000,
.prediv = 1,
.mult = 17,
.postdiv = 1,
.cvdd_min = 1300000,
.cvdd_max = 1350000,
};
static const struct da850_opp da850_opp_372 = {
.freq = 372000,
.prediv = 2,
.mult = 31,
.postdiv = 1,
.cvdd_min = 1200000,
.cvdd_max = 1320000,
};
static const struct da850_opp da850_opp_300 = {
.freq = 300000,
.prediv = 1,
@ -876,6 +902,9 @@ static const struct da850_opp da850_opp_96 = {
}
static struct cpufreq_frequency_table da850_freq_table[] = {
OPP(456),
OPP(408),
OPP(372),
OPP(300),
OPP(200),
OPP(96),
@ -885,6 +914,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
},
};
#ifdef CONFIG_REGULATOR
static int da850_set_voltage(unsigned int index);
static int da850_regulator_init(void);
#endif
static struct davinci_cpufreq_config cpufreq_info = {
.freq_table = da850_freq_table,
#ifdef CONFIG_REGULATOR
.init = da850_regulator_init,
.set_voltage = da850_set_voltage,
#endif
};
#ifdef CONFIG_REGULATOR
static struct regulator *cvdd;
@ -895,7 +937,7 @@ static int da850_set_voltage(unsigned int index)
if (!cvdd)
return -ENODEV;
opp = (struct da850_opp *) da850_freq_table[index].index;
opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
}
@ -912,14 +954,6 @@ static int da850_regulator_init(void)
}
#endif
static struct davinci_cpufreq_config cpufreq_info = {
.freq_table = &da850_freq_table[0],
#ifdef CONFIG_REGULATOR
.init = da850_regulator_init,
.set_voltage = da850_set_voltage,
#endif
};
static struct platform_device da850_cpufreq_device = {
.name = "cpufreq-davinci",
.dev = {
@ -928,12 +962,22 @@ static struct platform_device da850_cpufreq_device = {
.id = -1,
};
unsigned int da850_max_speed = 300000;
int __init da850_register_cpufreq(char *async_clk)
{
int i;
/* cpufreq driver can help keep an "async" clock constant */
if (async_clk)
clk_add_alias("async", da850_cpufreq_device.name,
async_clk, NULL);
for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
if (da850_freq_table[i].frequency <= da850_max_speed) {
cpufreq_info.freq_table = &da850_freq_table[i];
break;
}
}
return platform_device_register(&da850_cpufreq_device);
}
@ -942,17 +986,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
{
int i, ret = 0, diff;
unsigned int best = (unsigned int) -1;
struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
rate /= 1000; /* convert to kHz */
for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
diff = da850_freq_table[i].frequency - rate;
for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
diff = table[i].frequency - rate;
if (diff < 0)
diff = -diff;
if (diff < best) {
best = diff;
ret = da850_freq_table[i].frequency;
ret = table[i].frequency;
}
}
@ -973,7 +1018,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
struct pll_data *pll = clk->pll_data;
int ret;
opp = (struct da850_opp *) da850_freq_table[index].index;
opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
prediv = opp->prediv;
mult = opp->mult;
postdiv = opp->postdiv;

15
arch/arm/mach-davinci/devices-tnetv107x.c
View File

@ -344,7 +344,20 @@ static struct platform_device tsc_device = {
void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
{
int i;
int i, error;
struct clk *tsc_clk;
/*
* The reset defaults for tnetv107x tsc clock divider is set too high.
* This forces the clock down to a range that allows the ADC to
* complete sample conversion in time.
*/
tsc_clk = clk_get(NULL, "sys_tsc_clk");
if (tsc_clk) {
error = clk_set_rate(tsc_clk, 5000000);
WARN_ON(error < 0);
clk_put(tsc_clk);
}
platform_device_register(&edma_device);
platform_device_register(&tnetv107x_wdt_device);

7
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -27,6 +27,13 @@
extern void __iomem *da8xx_syscfg0_base;
extern void __iomem *da8xx_syscfg1_base;
/*
* If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
* (than the regular 300Mhz variant), the board code should set this up
* with the supported speed before calling da850_register_cpufreq().
*/
extern unsigned int da850_max_speed;
/*
* The cp_intc interrupt controller for the da8xx isn't in the same
* chunk of physical memory space as the other registers (like it is

7
arch/arm/mach-davinci/psc.c
View File

@ -83,19 +83,14 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
pdctl1 = __raw_readl(psc_base + PDCTL1);
pdctl1 |= 0x100;
__raw_writel(pdctl1, psc_base + PDCTL1);
do {
ptstat = __raw_readl(psc_base +
PTSTAT);
} while (!(((ptstat >> domain) & 1) == 0));
} else {
ptcmd = 1 << domain;
__raw_writel(ptcmd, psc_base + PTCMD);
}
do {
ptstat = __raw_readl(psc_base + PTSTAT);
} while (!(((ptstat >> domain) & 1) == 0));
}
do {
mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);

24
arch/arm/mach-davinci/time.c
View File

@ -272,13 +272,34 @@ static cycle_t read_cycles(struct clocksource *cs)
return (cycles_t)timer32_read(t);
}
/*
* Kernel assumes that sched_clock can be called early but may not have
* things ready yet.
*/
static cycle_t read_dummy(struct clocksource *cs)
{
return 0;
}
static struct clocksource clocksource_davinci = {
.rating = 300,
.read = read_cycles,
.read = read_dummy,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/*
* Overwrite weak default sched_clock with something more precise
*/
unsigned long long notrace sched_clock(void)
{
const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
clocksource_davinci.shift);
}
/*
* clockevent
*/
@ -376,6 +397,7 @@ static void __init davinci_timer_init(void)
davinci_clock_tick_rate = clk_get_rate(timer_clk);
/* setup clocksource */
clocksource_davinci.read = read_cycles;
clocksource_davinci.name = id_to_name[clocksource_id];
if (clocksource_register_hz(&clocksource_davinci,
davinci_clock_tick_rate))

13
arch/arm/mach-davinci/tnetv107x.c
View File

@ -133,10 +133,11 @@ define_pll_clk(eth, 2, 0x0ff, 0x400);
/* Level 2 - divided outputs from the PLLs */
#define define_pll_div_clk(pll, cname, div) \
static struct clk pll##_##cname##_clk = { \
.name = #pll "_" #cname "_clk",\
.name = #pll "_" #cname "_clk", \
.parent = &pll_##pll##_clk, \
.flags = CLK_PLL, \
.div_reg = PLLDIV##div, \
.set_rate = davinci_set_sysclk_rate, \
}
define_pll_div_clk(sys, arm1176, 1);
@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM);
lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST);
lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST);
lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM);
lpsc_clk_enabled(timer1, sys_half_clk, TIMER1);
lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE);
lpsc_clk(ethss, eth_125mhz_clk, ETHSS);
@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO);
lpsc_clk(sdio0, sys_half_clk, SDIO0);
lpsc_clk(sdio1, sys_half_clk, SDIO1);
lpsc_clk(timer0, sys_half_clk, TIMER0);
lpsc_clk(timer1, sys_half_clk, TIMER1);
lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP);
lpsc_clk(ssp, sys_half_clk, SSP);
lpsc_clk(tdm0, tdm_0_clk, TDM0);
lpsc_clk(tdm1, tdm_1_clk, TDM1);
lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ);
lpsc_clk(mcdma, sys_half_clk, MCDMA);
lpsc_clk(usb0, sys_half_clk, USB0);
lpsc_clk(usb1, sys_half_clk, USB1);
lpsc_clk(usbss, sys_half_clk, USBSS);
lpsc_clk(usb0, clk_usbss, USB0);
lpsc_clk(usb1, clk_usbss, USB1);
lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII);
lpsc_clk(imcop, sys_dsp_clk, IMCOP);
lpsc_clk(spare, sys_half_clk, SPARE);
@ -281,7 +282,9 @@ static struct clk_lookup clks[] = {
CLK(NULL, "clk_tdm0", &clk_tdm0),
CLK(NULL, "clk_vlynq", &clk_vlynq),
CLK(NULL, "clk_mcdma", &clk_mcdma),
CLK(NULL, "clk_usbss", &clk_usbss),
CLK(NULL, "clk_usb0", &clk_usb0),
CLK(NULL, "clk_usb1", &clk_usb1),
CLK(NULL, "clk_tdm1", &clk_tdm1),
CLK(NULL, "clk_debugss", &clk_debugss),
CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii),
@ -289,8 +292,6 @@ static struct clk_lookup clks[] = {
CLK(NULL, "clk_imcop", &clk_imcop),
CLK(NULL, "clk_spare", &clk_spare),
CLK("davinci_mmc.1", NULL, &clk_sdio1),
CLK(NULL, "clk_usb1", &clk_usb1),
CLK(NULL, "clk_usbss", &clk_usbss),
CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
CLK(NULL, NULL, NULL),

6
arch/arm/mach-dove/Kconfig
View File

@ -9,6 +9,12 @@ config MACH_DOVE_DB
Say 'Y' here if you want your kernel to support the
Marvell DB-MV88AP510 Development Board.
config MACH_CM_A510
bool "CompuLab CM-A510 Board"
help
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
endmenu
endif

3
arch/arm/mach-dove/Makefile
View File

@ -1,3 +1,4 @@
obj-y += common.o addr-map.o irq.o pcie.o
obj-y += common.o addr-map.o irq.o pcie.o mpp.o
obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_CM_A510) += cm-a510.o

95
arch/arm/mach-dove/cm-a510.c Normal file
View File

@ -0,0 +1,95 @@
/*
* arch/arm/mach-dove/cm-a510.c
*
* Copyright (C) 2010 CompuLab, Ltd.
* Konstantin Sinyuk <kostyas@compulab.co.il>
*
* Based on Marvell DB-MV88AP510-BP Development Board Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dove.h>
#include "common.h"
static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
};
static struct mv_sata_platform_data cm_a510_sata_data = {
.n_ports = 1,
};
/*
* SPI Devices:
* SPI0: 1M Flash Winbond w25q32bv
*/
static const struct flash_platform_data cm_a510_spi_flash_data = {
.type = "w25q32bv",
};
static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
{
.modalias = "m25p80",
.platform_data = &cm_a510_spi_flash_data,
.irq = -1,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
},
};
static int __init cm_a510_pci_init(void)
{
if (machine_is_cm_a510())
dove_pcie_init(1, 1);
return 0;
}
subsys_initcall(cm_a510_pci_init);
/* Board Init */
static void __init cm_a510_init(void)
{
/*
* Basic Dove setup. Needs to be called early.
*/
dove_init();
dove_ge00_init(&cm_a510_ge00_data);
dove_ehci0_init();
dove_ehci1_init();
dove_sata_init(&cm_a510_sata_data);
dove_sdio0_init();
dove_sdio1_init();
dove_spi0_init();
dove_spi1_init();
dove_uart0_init();
dove_uart1_init();
dove_i2c_init();
spi_register_board_info(cm_a510_spi_flash_info,
ARRAY_SIZE(cm_a510_spi_flash_info));
}
MACHINE_START(CM_A510, "Compulab CM-A510 Board")
.boot_params = 0x00000100,
.init_machine = cm_a510_init,
.map_io = dove_map_io,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END

9
arch/arm/mach-dove/include/mach/dove.h
View File

@ -131,14 +131,21 @@
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
#define DOVE_NAND_GPIO_EN (1 << 0)
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
#define DOVE_SPI_GPIO_SEL (1 << 5)
#define DOVE_UART1_GPIO_SEL (1 << 4)
#define DOVE_AU1_GPIO_SEL (1 << 3)
#define DOVE_CAM_GPIO_SEL (1 << 2)
#define DOVE_SD1_GPIO_SEL (1 << 1)
#define DOVE_SD0_GPIO_SEL (1 << 0)
/* Power Management */
#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
/* Real Time Clock */
#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)

6
arch/arm/mach-dove/include/mach/gpio.h
View File

@ -14,12 +14,14 @@
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define GPIO_MAX 64
#define GPIO_MAX 72
#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
((pin < 64) ? GPIO_BASE_HI : \
DOVE_GPIO2_VIRT_BASE))
#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)

212
arch/arm/mach-dove/mpp.c Normal file
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@ -0,0 +1,212 @@
/*
* arch/arm/mach-dove/mpp.c
*
* MPP functions for Marvell Dove SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/dove.h>
#include "mpp.h"
#define MPP_NR_REGS 4
#define MPP_CTRL(i) ((i) == 3 ? \
DOVE_MPP_CTRL4_VIRT_BASE : \
DOVE_MPP_VIRT_BASE + (i) * 4)
#define PMU_SIG_REGS 2
#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
struct dove_mpp_grp {
int start;
int end;
};
static struct dove_mpp_grp dove_mpp_grp[] = {
[MPP_24_39] = {
.start = 24,
.end = 39,
},
[MPP_40_45] = {
.start = 40,
.end = 45,
},
[MPP_46_51] = {
.start = 40,
.end = 45,
},
[MPP_58_61] = {
.start = 58,
.end = 61,
},
[MPP_62_63] = {
.start = 62,
.end = 63,
},
};
static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
{
int i;
for (i = start; i <= end; i++)
orion_gpio_set_valid(i, gpio_mode);
}
static void dove_mpp_dump_regs(void)
{
#ifdef DEBUG
int i;
pr_debug("MPP_CTRL regs:");
for (i = 0; i < MPP_NR_REGS; i++)
printk(" %08x", readl(MPP_CTRL(i)));
printk("\n");
pr_debug("PMU_SIG_CTRL regs:");
for (i = 0; i < PMU_SIG_REGS; i++)
printk(" %08x", readl(PMU_SIG_CTRL(i)));
printk("\n");
pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
#endif
}
static void dove_mpp_cfg_nfc(int sel)
{
u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
mpp_gen_cfg &= ~0x1;
mpp_gen_cfg |= sel;
writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
}
static void dove_mpp_cfg_au1(int sel)
{
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
if (!sel || sel == 0x2)
dove_mpp_gpio_mode(52, 57, 0);
else
dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
if (sel & 0x1) {
global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
dove_mpp_gpio_mode(56, 57, 0);
}
if (sel & 0x2) {
mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
}
if (sel & 0x4) {
ssp_ctrl1 |= DOVE_SSP_ON_AU1;
dove_mpp_gpio_mode(52, 55, 0);
}
if (sel & 0x8)
mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
}
static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
{
int start = dove_mpp_grp[num].start;
int end = dove_mpp_grp[num].end;
int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
*mpp_ctrl &= ~(0x1 << num);
*mpp_ctrl |= sel << num;
dove_mpp_gpio_mode(start, end, gpio_mode);
}
void __init dove_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
u32 pmu_mpp_ctrl = 0;
u32 pmu_sig_ctrl[PMU_SIG_REGS];
int i;
/* Initialize gpiolib. */
orion_gpio_init();
for (i = 0; i < MPP_NR_REGS; i++)
mpp_ctrl[i] = readl(MPP_CTRL(i));
for (i = 0; i < PMU_SIG_REGS; i++)
pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
dove_mpp_dump_regs();
for ( ; *mpp_list != MPP_END; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
pr_err("dove: invalid MPP number (%u)\n", num);
continue;
}
if (*mpp_list & MPP_NFC_MASK) {
dove_mpp_cfg_nfc(sel);
continue;
}
if (*mpp_list & MPP_AU1_MASK) {
dove_mpp_cfg_au1(sel);
continue;
}
if (*mpp_list & MPP_GRP_MASK) {
dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
continue;
}
shift = (num & 7) << 2;
if (*mpp_list & MPP_PMU_MASK) {
pmu_mpp_ctrl |= (0x1 << num);
pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
pmu_sig_ctrl[num / 8] |= 0xf << shift;
gpio_mode = 0;
} else {
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
}
orion_gpio_set_valid(num, gpio_mode);
}
for (i = 0; i < MPP_NR_REGS; i++)
writel(mpp_ctrl[i], MPP_CTRL(i));
for (i = 0; i < PMU_SIG_REGS; i++)
writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
dove_mpp_dump_regs();
}

220
arch/arm/mach-dove/mpp.h Normal file
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@ -0,0 +1,220 @@
#ifndef __ARCH_DOVE_MPP_CODED_H
#define __ARCH_DOVE_MPP_CODED_H
#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
/* MPP/group number */ ((_num) & 0xff) | \
/* MPP select value */ (((_mode) & 0xf) << 8) | \
/* MPP PMU */ ((!!(_pmu)) << 12) | \
/* group flag */ ((!!(_grp)) << 13) | \
/* AU1 flag */ ((!!(_au1)) << 14) | \
/* NFCE flag */ ((!!(_nfc)) << 15))
#define MPP_MAX 71
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
#define MPP_PMU_DRIVE_0 0x1
#define MPP_PMU_DRIVE_1 0x2
#define MPP_PMU_SDI 0x3
#define MPP_PMU_CPU_PWRDWN 0x4
#define MPP_PMU_STBY_PWRDWN 0x5
#define MPP_PMU_CORE_PWR_GOOD 0x8
#define MPP_PMU_BAT_FAULT 0xa
#define MPP_PMU_EXT0_WU 0xb
#define MPP_PMU_EXT1_WU 0xc
#define MPP_PMU_EXT2_WU 0xd
#define MPP_PMU_BLINK 0xe
#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
#define MPP0_GPIO0 MPP_PIN(0, 0x0)
#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
#define MPP1_GPIO1 MPP_PIN(1, 0x0)
#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
#define MPP2_GPIO2 MPP_PIN(2, 0x0)
#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
#define MPP3_GPIO3 MPP_PIN(3, 0x0)
#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
#define MPP4_GPIO4 MPP_PIN(4, 0x0)
#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
#define MPP5_GPIO5 MPP_PIN(5, 0x0)
#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
#define MPP6_GPIO6 MPP_PIN(6, 0x0)
#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
#define MPP7_GPIO7 MPP_PIN(7, 0x0)
#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
#define MPP8_GPIO8 MPP_PIN(8, 0x0)
#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
#define MPP9_GPIO9 MPP_PIN(9, 0x0)
#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
#define MPP10_GPIO10 MPP_PIN(10, 0x0)
#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
#define MPP11_GPIO11 MPP_PIN(11, 0x0)
#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
#define MPP12_GPIO12 MPP_PIN(12, 0x0)
#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
#define MPP13_GPIO13 MPP_PIN(13, 0x0)
#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
#define MPP14_GPIO14 MPP_PIN(14, 0x0)
#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
#define MPP15_GPIO15 MPP_PIN(15, 0x0)
#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
#define MPP16_GPIO16 MPP_PIN(16, 0x0)
#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
#define MPP17_GPIO17 MPP_PIN(17, 0x0)
#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
#define MPP18_GPIO18 MPP_PIN(18, 0x0)
#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
#define MPP19_GPIO19 MPP_PIN(19, 0x0)
#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
#define MPP20_GPIO20 MPP_PIN(20, 0x0)
#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
#define MPP21_GPIO21 MPP_PIN(21, 0x0)
#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
#define MPP22_GPIO22 MPP_PIN(22, 0x0)
#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
#define MPP23_GPIO23 MPP_PIN(23, 0x0)
#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
/* for MPP groups _num is a group index */
enum dove_mpp_grp_idx {
MPP_24_39 = 2,
MPP_40_45 = 0,
MPP_46_51 = 1,
MPP_58_61 = 5,
MPP_62_63 = 4,
};
#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
/* The MPP[64:71] control differs from other groups */
#define MPP64_71_GPO MPP_GRP_NFC(0x1)
#define MPP64_71_NFC MPP_GRP_NFC(0x0)
/*
* The MPP[52:57] functionality is encoded by 4 bits in different
* registers. The _num field in this case encodes those bits in
* correspodence with Table 135 of 88AP510 Functional specification
*/
#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
void dove_mpp_conf(unsigned int *mpp_list);
#endif /* __ARCH_DOVE_MPP_CODED_H */

138
arch/arm/mach-imx/Kconfig
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@ -1,13 +1,37 @@
config IMX_HAVE_DMA_V1
bool
if ARCH_MX1
config SOC_IMX1
bool
select CPU_ARM920T
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX21
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX25
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V2
select ARCH_MXC_IOMUX_V3
select MXC_AVIC
config SOC_IMX27
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
if ARCH_MX1
comment "MX1 platforms:"
config MACH_MXLADS
@ -31,33 +55,17 @@ endif
if ARCH_MX2
config SOC_IMX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
choice
prompt "CPUs:"
default MACH_MX21
config MACH_MX21
bool "i.MX21 support"
select SOC_IMX21
help
This enables support for Freescale's MX2 based i.MX21 processor.
config MACH_MX27
bool "i.MX27 support"
select SOC_IMX27
help
This enables support for Freescale's MX2 based i.MX27 processor.
@ -71,7 +79,10 @@ comment "MX21 platforms:"
config MACH_MX21ADS
bool "MX21ADS platform"
select SOC_IMX21
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for MX21ADS platform. This includes specific
@ -79,24 +90,79 @@ config MACH_MX21ADS
endif
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif
if MACH_MX27
comment "MX27 platforms:"
config MACH_MX27ADS
bool "MX27ADS platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
help
Include support for MX27ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -109,8 +175,9 @@ choice
default MACH_PCM970_BASEBOARD
config MACH_PCM970_BASEBOARD
prompt "PHYTEC PCM970 development board"
bool
bool "PHYTEC PCM970 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds board specific devices that can be found on Phytec's
PCM970 evaluation board.
@ -119,9 +186,14 @@ endchoice
config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX27 platform. This includes
@ -130,6 +202,7 @@ config MACH_CPUIMX27
config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_CPUIMX27
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds support for the internal SDHC2 used on CPUIMX27
for wifi or eMMC.
@ -148,8 +221,11 @@ choice
config MACH_EUKREA_MBIMX27_BASEBOARD
bool "Eukrea MBIMX27 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
help
This adds board specific devices that can be found on Eukrea's
@ -159,15 +235,26 @@ endchoice
config MACH_MX27_3DS
bool "MX27PDK platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_EHCI
help
Include support for Visstrim_m10 platform and its different variants.
This includes specific configurations for the board and its
@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX27 LITEKIT platform. This includes specific
@ -182,10 +270,17 @@ config MACH_IMX27LITE
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -194,8 +289,11 @@ config MACH_PCA100
config MACH_MXT_TD60
bool "Maxtrack i-MXT TD60"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for i-MXT (aka td60) platform. This

8
arch/arm/mach-imx/Makefile
View File

@ -4,13 +4,13 @@
# Object file lists.
obj-y := devices.o
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o

4
arch/arm/mach-imx/Makefile.boot
View File

@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000
params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000

2
arch/arm/mach-imx/clock-imx21.c
View File

@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "brom", brom_clk)
_REGISTER_CLOCK(NULL, "emma", emma_clk[0])
_REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)

2
arch/arm/mach-mx25/clock.c → arch/arm/mach-imx/clock-imx25.c
View File

@ -295,7 +295,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)

24
arch/arm/mach-imx/clock-imx27.c
View File

@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
if (clk->parent == parent)
return 0;
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
if (parent == &mpll_main1_clk) {
cscr |= CCM_CSCR_ARM_SRC;
} else {
@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
div--;
reg = __raw_readl(CCM_CSCR);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
reg &= ~(3 << 12);
reg |= div << 12;
reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
pdf += 4; /* MX27 TO2+ */
else
pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
else
nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
parent_rate = clk_get_rate(clk->parent);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
vpu_pdf += 4;
} else {
@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
* clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
* clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
*/
if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
return 2UL * parent_rate / 3UL;
return parent_rate;
@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
/* On TO2 we have to write the value back. Otherwise we
* read 0 from this register the next time.
*/
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
__raw_writel(reg, CCM_SPCTL0);
return mxc_decode_pll(reg, rate);
@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
u32 div;
unsigned long rate;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
else
div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
{
unsigned long rate, bclk_pdf;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
else
bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
{
unsigned long rate, ipg_pdf;
if (mx27_revision() >= CHIP_REV_2_0)
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
return clk_get_rate(clk->parent);
else
ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
_REGISTER_CLOCK(NULL, "ata", ata_clk)
_REGISTER_CLOCK(NULL, "mstick", mstick_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
{
unsigned long cscr = __raw_readl(CCM_CSCR);
if (mx27_revision() >= CHIP_REV_2_0) {
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
if (cscr & CCM_CSCR_ARM_SRC)
cpu_clk.parent = &mpll_main1_clk;

14
arch/arm/mach-imx/cpu-imx27.c
View File

@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
+ SYS_CHIP_ID));
cpu_silicon_rev = (int)(val >> 28);
switch (val >> 28) {
case 0:
cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
break;
case 1:
cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
break;
case 2:
cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
break;
default:
cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
}
cpu_partnumber = (int)((val >> 12) & 0xFFFF);
}

24
arch/arm/mach-imx/devices-imx21.h
View File

@ -9,10 +9,26 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)

51
arch/arm/mach-mx25/devices-imx25.h → arch/arm/mach-imx/devices-imx25.h
View File

@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
#define imx25_add_flexcan0(pdata) \
imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
#define imx25_add_flexcan1(pdata) \
imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c(id, pdata) \
@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst;
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
#define imx25_add_esdhc(id, pdata) \
imx_add_esdhc(&imx25_esdhc_data[id], pdata)

35
arch/arm/mach-imx/devices-imx27.h
View File

@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)

553
arch/arm/mach-imx/devices.c
View File

@ -1,553 +0,0 @@
/*
* Author: MontaVista Software, Inc.
* <source@mvista.com>
*
* Based on the OMAP devices.c
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include "devices.h"
#if defined(CONFIG_ARCH_MX1)
static struct resource imx1_camera_resources[] = {
{
.start = 0x00224000,
.end = 0x00224010,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CSI_INT,
.end = MX1_CSI_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
struct platform_device imx1_camera_device = {
.name = "mx1-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &imx1_camera_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = imx1_camera_resources,
.num_resources = ARRAY_SIZE(imx1_camera_resources),
};
static struct resource imx_rtc_resources[] = {
{
.start = 0x00204000,
.end = 0x00204024,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_RTC_INT,
.end = MX1_RTC_INT,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_RTC_SAMINT,
.end = MX1_RTC_SAMINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device = {
.name = "rtc-imx",
.id = 0,
.resource = imx_rtc_resources,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
};
static struct resource imx_wdt_resources[] = {
{
.start = 0x00201000,
.end = 0x00201008,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_WDT_INT,
.end = MX1_WDT_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_wdt_device = {
.name = "imx-wdt",
.id = 0,
.resource = imx_wdt_resources,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
};
static struct resource imx_usb_resources[] = {
{
.start = 0x00212000,
.end = 0x00212148,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_USBD_INT0,
.end = MX1_USBD_INT0,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT1,
.end = MX1_USBD_INT1,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT2,
.end = MX1_USBD_INT2,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT3,
.end = MX1_USBD_INT3,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT4,
.end = MX1_USBD_INT4,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT5,
.end = MX1_USBD_INT5,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT6,
.end = MX1_USBD_INT6,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_usb_device = {
.name = "imx_udc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_usb_resources),
.resource = imx_usb_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
.irq = MX1_GPIO_INT_PORTA,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
.irq = MX1_GPIO_INT_PORTB,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
.irq = MX1_GPIO_INT_PORTC,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
.irq = MX1_GPIO_INT_PORTD,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx1_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
#ifdef CONFIG_MACH_MX27
static struct resource mx27_camera_resources[] = {
{
.start = MX27_CSI_BASE_ADDR,
.end = MX27_CSI_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_EMMA_PRP_BASE_ADDR,
.end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_CSI,
.end = MX27_INT_CSI,
.flags = IORESOURCE_IRQ,
},{
.start = MX27_INT_EMMAPRP,
.end = MX27_INT_EMMAPRP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx27_camera_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx27_camera_resources),
.resource = mx27_camera_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
#endif
/*
* General Purpose Timer
* - i.MX21: 3 timers
* - i.MX27: 6 timers
*/
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
static struct resource timer ## n ##_resources[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
} \
}; \
\
struct platform_device mxc_gpt ## n = { \
.name = "imx_gpt", \
.id = n, \
.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
.resource = timer ## n ## _resources, \
}
/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif
/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
{
.start = MX2x_WDOG_BASE_ADDR,
.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mxc_w1_master_resources[] = {
{
.start = MX2x_OWIRE_BASE_ADDR,
.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
/*
* lcdc:
* - i.MX1: the basic controller
* - i.MX21: to be checked
* - i.MX27: like i.MX1, with slightly variations
*/
static struct resource mxc_fb[] = {
{
.start = MX2x_LCDC_BASE_ADDR,
.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_LCDC,
.end = MX2x_INT_LCDC,
.flags = IORESOURCE_IRQ,
}
};
/* mxc lcd driver */
struct platform_device mxc_fb_device = {
.name = "imx-fb",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fb),
.resource = mxc_fb,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource mxc_pwm_resources[] = {
{
.start = MX2x_PWM_BASE_ADDR,
.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_PWM,
.end = MX2x_INT_PWM,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources),
.resource = mxc_pwm_resources,
};
#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
static struct resource mxc_sdhc_resources ## n[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
}, { \
.start = dmareq, \
.end = dmareq, \
.flags = IORESOURCE_DMA, \
}, \
}; \
\
static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
\
struct platform_device mxc_sdhc_device ## n = { \
.name = "mxc-mmc", \
.id = n, \
.dev = { \
.dma_mask = &mxc_sdhc ## n ## _dmamask, \
.coherent_dma_mask = DMA_BIT_MASK(32), \
}, \
.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
.resource = mxc_sdhc_resources ## n, \
}
DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR,
.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB3,
.end = MX27_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh1_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x200,
.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB1,
.end = MX27_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x400,
.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB2,
.end = MX27_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif
/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ \
.chip.label = "gpio-" #n, \
.irq = _irq, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORT(SOC, n) \
{ \
.chip.label = "gpio-" #n, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
DEFINE_MXC_GPIO_PORT(SOC, 1), \
DEFINE_MXC_GPIO_PORT(SOC, 2), \
DEFINE_MXC_GPIO_PORT(SOC, 3), \
DEFINE_MXC_GPIO_PORT(SOC, 4), \
DEFINE_MXC_GPIO_PORT(SOC, 5), \
}
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
int __init imx21_register_gpios(void)
{
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
int __init imx27_register_gpios(void)
{
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
{
.start = MX21_USBOTG_BASE_ADDR,
.end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MX21_INT_USBHOST,
.end = MX21_INT_USBHOST,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx21_usbhc_device = {
.name = "imx21-hcd",
.id = 0,
.dev = {
.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
.resource = mx21_usbhc_resources,
};
#endif
static struct resource imx_kpp_resources[] = {
{
.start = MX2x_KPP_BASE_ADDR,
.end = MX2x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX2x_INT_KPP,
.end = MX2x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
#endif

29
arch/arm/mach-imx/devices.h
View File

@ -1,29 +0,0 @@
#ifdef CONFIG_ARCH_MX1
extern struct platform_device imx1_camera_device;
extern struct platform_device imx_rtc_device;
extern struct platform_device imx_wdt_device;
extern struct platform_device imx_usb_device;
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_gpt3;
extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5;
#endif
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mx27_camera_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mx21_usbhc_device;
extern struct platform_device imx_kpp_device;
#endif

4
arch/arm/mach-imx/dma-v1.c
View File

@ -818,9 +818,11 @@ static int __init imx_dma_init(void)
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
#endif
BUG();
return 0;
dma_clk = clk_get(NULL, "dma");
if (IS_ERR(dma_clk))
return PTR_ERR(dma_clk);
clk_enable(dma_clk);
/* reset DMA module */

17
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -26,20 +26,16 @@
#include <linux/spi/ads7846.h>
#include <linux/backlight.h>
#include <video/platform_lcd.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_mbimx27_pins[] __initconst = {
/* UART2 */
@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = {
KEY(1, 1, KEY_LEFT),
};
static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
static const struct matrix_keymap_data
eukrea_mbimx27_keymap_data __initconst = {
.keymap = eukrea_mbimx27_keymap,
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
.mode = eukrea_mbimx27_modes,
.num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = {
&leds_gpio,
};
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.dat3_card_detect = 1,
};
@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_uart3(&uart_pdata);
#endif
mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
imx27_add_mxc_mmc(0, &sdhc_pdata);
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
gpio_request(GPIO_PORTA | 25, "lcd_enable");
platform_device_register(&eukrea_mbimx27_lcd_powerdev);
mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

10
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c → arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View File

@ -33,13 +33,11 @@
#include <asm/mach/arch.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/audmux.h>
#include "devices-imx25.h"
#include "devices.h"
static struct pad_desc eukrea_mbimxsd_pads[] = {
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
MX25_PAD_LD0__LD0,
MX25_PAD_LD1__LD1,
@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
.mode = eukrea_mximxsd_modes,
.num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
.pwmr = 0x00A903FF,
@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
#endif
imx25_add_imx_uart1(&uart_pdata);
mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx25_add_flexcan1(NULL);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);

21
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -28,7 +28,6 @@
#include <linux/serial_8250.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -40,11 +39,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_cpuimx27_pins[] __initconst = {
/* UART1 */
@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_wdt,
&mxc_w1_master_device,
};
static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
@ -215,18 +210,18 @@ static struct platform_device serial_device = {
#endif
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void)
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
mxc_register_device(&mxc_sdhc_device1, NULL);
imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();

19
arch/arm/mach-mx25/mach-cpuimx25.c → arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View File

@ -26,7 +26,6 @@
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/hardware.h>
@ -39,17 +38,15 @@
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mxc_ehci.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct pad_desc eukrea_cpuimx25_pads[] = {
static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
/* FEC - RMII */
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
},
};
static struct mxc_usbh_platform_data otg_pdata = {
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_uart0(&uart_pdata);
imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_fec(&mx25_fec_pdata);
i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
if (otg_mode_host)
mxc_register_device(&mxc_otg, &otg_pdata);
imx25_add_mxc_ehci_otg(&otg_pdata);
else
mxc_register_device(&otg_udc_device, &otg_device_pdata);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();

12
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View File

@ -34,12 +34,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/iomux.h>
#include <mach/mxc_ehci.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
free_irq(SDHC1_IRQ, data);
}
static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
.init = visstrim_m10_sdhc1_init,
.exit = visstrim_m10_sdhc1_exit,
};
@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
static const struct mxc_usbh_platform_data
visstrim_m10_usbotg_pdata __initconst = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void)
ARRAY_SIZE(visstrim_m10_i2c_devices));
imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

1
arch/arm/mach-imx/mach-imx27lite.c
View File

@ -25,7 +25,6 @@
#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mx27lite_pins[] __initconst = {
/* UART1 */

1
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -30,7 +30,6 @@
#include <mach/irqs.h>
#include "devices-imx1.h"
#include "devices.h"
static const int mx1ads_pins[] __initconst = {
/* UART1 */

20
arch/arm/mach-imx/mach-mx21ads.c
View File

@ -24,13 +24,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#include "devices-imx21.h"
#include "devices.h"
/*
* Memory-mapped I/O on MX21ADS base board
@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = {
},
};
static struct imx_fb_platform_data mx21ads_fb_data = {
static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
.mode = mx21ads_modes,
.num_modes = ARRAY_SIZE(mx21ads_modes),
@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
int ret;
ret = request_irq(IRQ_GPIOD(25), detect_irq,
return request_irq(IRQ_GPIOD(25), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
if (ret)
goto out;
return 0;
out:
return ret;
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOD(25), data);
}
static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
.get_ro = mx21ads_sdhc_get_ro,
.init = mx21ads_sdhc_init,
@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void)
imx21_add_imx_uart0(&uart_pdata_rts);
imx21_add_imx_uart2(&uart_pdata_norts);
imx21_add_imx_uart3(&uart_pdata_rts);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
imx21_add_imx_fb(&mx21ads_fb_data);
imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

32
arch/arm/mach-mx25/mach-mx25_3ds.c → arch/arm/mach-imx/mach-mx25_3ds.c
View File

@ -30,6 +30,7 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -39,17 +40,15 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct pad_desc mx25pdk_pads[] = {
static iomux_v3_cfg_t mx25pdk_pads[] = {
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = {
},
};
static struct imx_fb_platform_data mx25pdk_fb_pdata = {
static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
.mode = mx25pdk_modes,
.num_modes = ARRAY_SIZE(mx25pdk_modes),
.pwmr = 0x00A903FF,
@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = {
KEY(3, 3, KEY_POWER),
};
static struct matrix_keymap_data mx25pdk_keymap_data = {
static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
.keymap = mx25pdk_keymap,
.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
};
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERNAL_PHY,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
static void __init mx25pdk_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
ARRAY_SIZE(mx25pdk_pads));
imx25_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_usbh2, NULL);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
imx25_add_mxc_nand(&mx25pdk_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
mxc_register_device(&mxc_wdt, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_imx_fb(&mx25pdk_fb_pdata);
imx25_add_imx2_wdt(NULL);
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
}
static void __init mx25pdk_timer_init(void)

160
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -22,20 +22,27 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
#include <linux/irq.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/delay.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/mmc.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
#define SD1_EN_GPIO (GPIO_PORTB + 25)
#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
#define SPI2_SS0 (GPIO_PORTD + 21)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = {
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
/* OTG */
OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* CSPI2 */
PD22_PF_CSPI2_SCLK,
PD23_PF_CSPI2_MISO,
PD24_PF_CSPI2_MOSI,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = {
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx27_3ds_keymap_data = {
static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
.keymap = mx27_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(26), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27_3ds_sdhc1_init,
.exit = mx27_3ds_sdhc1_exit,
};
@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void)
gpio_direction_output(SD1_EN_GPIO, 1);
}
static int otg_phy_init(void)
{
gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
mdelay(1);
gpio_set_value(OTG_PHY_RESET_GPIO, 1);
return 0;
}
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init mx27_3ds_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", mx27_3ds_otg_mode);
/* Regulators */
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("lcd_2v8", NULL),
};
static struct regulator_init_data vmmc1_init = {
.constraints = {
.min_uV = 2800000,
.max_uV = 2800000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
.consumer_supplies = vmmc1_consumers,
};
static struct regulator_consumer_supply vgen_consumers[] = {
REGULATOR_SUPPLY("vdd_lcdio", NULL),
};
static struct regulator_init_data vgen_init = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
.consumer_supplies = vgen_consumers,
};
static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
{
.id = MC13783_REGU_VMMC1,
.init_data = &vmmc1_init,
}, {
.id = MC13783_REGU_VGEN,
.init_data = &vgen_init,
},
};
/* MC13783 */
static struct mc13783_platform_data mc13783_pdata __initdata = {
.regulators = mx27_3ds_regulators,
.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
.flags = MC13783_USE_REGULATOR,
};
/* SPI */
static int spi2_internal_chipselect[] = {SPI2_SS0};
static const struct spi_imx_master spi2_pdata __initconst = {
.chipselect = spi2_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
};
static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
{
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
.irq = IRQ_GPIOC(14),
.mode = SPI_CS_HIGH,
},
};
static void __init mx27pdk_init(void)
{
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@ -128,8 +258,24 @@ static void __init mx27pdk_init(void)
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_keypad(&mx27_3ds_keymap_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_imx2_wdt(NULL);
otg_phy_init();
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
#endif
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
imx27_add_spi_imx1(&spi2_pdata);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
}
static void __init mx27pdk_timer_init(void)

17
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -30,11 +30,8 @@
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
/*
* Base address of PBC controller, CS4
@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = {
},
};
static struct imx_fb_platform_data mx27ads_fb_data = {
static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
.mode = mx27ads_modes,
.num_modes = ARRAY_SIZE(mx27ads_modes),
@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(7), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27ads_sdhc1_init,
.exit = mx27ads_sdhc1_exit,
};
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.init = mx27ads_sdhc2_init,
.exit = mx27ads_sdhc2_exit,
};
static struct platform_device *platform_devices[] __initdata = {
&mx27ads_nor_mtd_device,
&mxc_w1_master_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void)
i2c_register_board_info(1, mx27ads_i2c_devices,
ARRAY_SIZE(mx27ads_i2c_devices));
imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
imx27_add_imx_fb(&mx27ads_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_mxc_mmc(1, &sdhc2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_mxc_w1(NULL);
}
static void __init mx27ads_timer_init(void)

11
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -31,11 +31,8 @@
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mxt_td60_pins[] __initconst = {
/* UART0 */
@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = {
},
};
static struct imx_fb_platform_data mxt_td60_fb_data = {
static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
.mode = mxt_td60_modes,
.num_modes = ARRAY_SIZE(mxt_td60_modes),
@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOF(8), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mxt_td60_sdhc1_init,
.exit = mxt_td60_sdhc1_exit,
};
@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void)
imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_fb(&mxt_td60_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_fec(NULL);
}

33
arch/arm/mach-imx/mach-pca100.c
View File

@ -29,7 +29,6 @@
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -40,13 +39,9 @@
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/imxfb.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = {
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_wdt,
};
static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
.bitrate = 100000,
};
@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOC(29), data);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.init = pca100_sdhc2_init,
.exit = pca100_sdhc2_exit,
};
@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = {
},
};
static struct imx_fb_platform_data pca100_fb_data = {
static const struct imx_fb_platform_data pca100_fb_data __initconst = {
.mode = pca100_fb_modes,
.num_modes = ARRAY_SIZE(pca100_fb_modes),
@ -389,7 +379,7 @@ static void __init pca100_init(void)
imx27_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
imx27_add_mxc_nand(&pca100_nand_board_info);
@ -417,23 +407,24 @@ static void __init pca100_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host) {
gpio_set_value(OTG_PHY_CS_GPIO, 0);
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
mxc_register_device(&mxc_fb_device, &pca100_fb_data);
imx27_add_imx_fb(&pca100_fb_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
}
static void __init pca100_timer_init(void)

12
arch/arm/mach-imx/mach-pcm038.c
View File

@ -37,11 +37,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int pcm038_pins[] __initconst = {
/* UART1 */
@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
&pcm038_sram_mtd_device,
&mxc_wdt,
};
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
static struct regulator_consumer_supply sdhc1_consumers[] = {
{
.dev = &mxc_sdhc_device1.dev,
.dev_name = "mxc-mmc.1",
.supply = "sdhc_vcc",
},
};
@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
}
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
@ -322,10 +318,12 @@ static void __init pcm038_init(void)
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#ifdef CONFIG_MACH_PCM970_BASEBOARD
pcm970_baseboard_init();

1
arch/arm/mach-imx/mach-scb9328.c
View File

@ -25,7 +25,6 @@
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
#include "devices.h"
/*
* This scb9328 has a 32MiB flash

7
arch/arm/mach-imx/mm-imx1.c
View File

@ -25,12 +25,7 @@
#include <mach/hardware.h>
static struct map_desc imx_io_desc[] __initdata = {
{
.virtual = MX1_IO_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
.length = MX1_IO_SIZE,
.type = MT_DEVICE
}
imx_map_entry(MX1, IO, MT_DEVICE),
};
void __init mx1_map_io(void)

21
arch/arm/mach-imx/mm-imx21.c
View File

@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX21_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
.length = MX21_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX21_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
.length = MX21_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
.length = MX21_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, X_MEMC, MT_DEVICE),
};
/*

27
arch/arm/mach-mx25/mm.c → arch/arm/mach-imx/mm-imx25.c
View File

@ -30,25 +30,12 @@
/*
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
* These are the mappings common across all MX25 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX25_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
.length = MX25_AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
.length = MX25_AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
.length = MX25_AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
static struct map_desc mx25_io_desc[] __initdata = {
imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
};
/*
@ -62,14 +49,14 @@ void __init mx25_map_io(void)
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
}
int imx25_register_gpios(void);
void __init mx25_init_irq(void)
{
mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
imx25_register_gpios();
}

21
arch/arm/mach-imx/mm-imx27.c
View File

@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX27_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
.length = MX27_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX27_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
.length = MX27_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
.length = MX27_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, X_MEMC, MT_DEVICE),
};
/*

12
arch/arm/mach-imx/pcm970-baseboard.c
View File

@ -25,11 +25,9 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include "devices.h"
#include "devices-imx27.h"
static const int pcm970_pins[] __initconst = {
/* SDHC */
@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data)
gpio_free(GPIO_PORTC + 28);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = pcm970_sdhc2_get_ro,
.init = pcm970_sdhc2_init,
.exit = pcm970_sdhc2_exit,
@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = {
},
};
static struct imx_fb_platform_data pcm038_fb_data = {
static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
.mode = pcm970_modes,
.num_modes = ARRAY_SIZE(pcm970_modes),
@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void)
mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
"PCM970");
mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
platform_device_register(&pcm970_sja1000);
}

3
arch/arm/mach-imx/pm-imx27.c
View File

@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = {
static int __init mx27_pm_init(void)
{
if (!cpu_is_mx27())
return 0;
suspend_set_ops(&mx27_suspend_ops);
return 0;
}

12
arch/arm/mach-kirkwood/Kconfig
View File

@ -45,18 +45,18 @@ config MACH_GURUPLUG
Marvell GuruPlug Reference Board.
config MACH_TS219
bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
help
Say 'Y' here if you want your kernel to support the
QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
devices.
QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
TS-219P+ Turbo NAS devices.
config MACH_TS41X
bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
help
Say 'Y' here if you want your kernel to support the
QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
devices.
QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
NAS devices.
config MACH_DOCKSTAR
bool "Seagate FreeAgent DockStar"

16
arch/arm/mach-kirkwood/ts219-setup.c
View File

@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
MPP11_UART0_RXD,
MPP13_UART1_TXD, /* PIC controller */
MPP14_UART1_RXD, /* PIC controller */
MPP15_GPIO, /* USB Copy button */
MPP16_GPIO, /* Reset button */
MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */
MPP16_GPIO, /* Reset button (on devices with 88F6281) */
MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
MPP37_GPIO, /* Reset button (on devices with 88F6282) */
MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */
MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
0
};
static void __init qnap_ts219_init(void)
{
u32 dev, rev;
/*
* Basic setup. Needs to be called early.
*/
@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void)
qnap_tsx1x_register_flash();
kirkwood_i2c_init();
i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6282_DEV_ID) {
qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
qnap_ts219_buttons[1].gpio = 37; /* Reset button */
qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
}
kirkwood_ge00_init(&qnap_ts219_ge00_data);
kirkwood_sata_init(&qnap_ts219_sata_data);
kirkwood_ehci_init();

9
arch/arm/mach-kirkwood/ts41x-setup.c
View File

@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
static void __init qnap_ts41x_init(void)
{
u32 dev, rev;
/*
* Basic setup. Needs to be called early.
*/
@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void)
qnap_tsx1x_register_flash();
kirkwood_i2c_init();
i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6282_DEV_ID) {
qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
}
kirkwood_ge00_init(&qnap_ts41x_ge00_data);
kirkwood_ge01_init(&qnap_ts41x_ge01_data);
kirkwood_sata_init(&qnap_ts41x_sata_data);
kirkwood_ehci_init();
platform_device_register(&qnap_ts41x_button_device);

22
arch/arm/mach-mmp/Kconfig
View File

@ -37,25 +37,38 @@ config MACH_TTC_DKB
Say 'Y' here if you want to support the Marvell PXA910-based
TTC_DKB Development Board.
config MACH_BROWNSTONE
bool "Marvell's Brownstone Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Brown Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv7 architecture.
config MACH_FLINT
bool "Marvell's Flint Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Flint Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv6 architecture.
ARMv7 architecture.
config MACH_MARVELL_JASPER
bool "Marvell's Jasper Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-base
Jasper Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv6 architecture.
ARMv7 architecture.
config MACH_TETON_BGA
bool "Marvell's PXA168 Teton BGA Development Board"
@ -80,8 +93,7 @@ config CPU_PXA910
config CPU_MMP2
bool
select CPU_V6
select CPU_32v6K
select CPU_PJ4
help
Select code specific to MMP2. MMP2 is ARMv6 compatible.
Select code specific to MMP2. MMP2 is ARMv7 compatible.
endif

1
arch/arm/mach-mmp/Makefile
View File

@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o

204
arch/arm/mach-mmp/brownstone.c Normal file
View File

@ -0,0 +1,204 @@
/*
* linux/arch/arm/mach-mmp/brownstone.c
*
* Support for the Marvell Brownstone Development Platform.
*
* Copyright (C) 2009-2010 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/max8649.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/max8925.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/addr-map.h>
#include <mach/mfp-mmp2.h>
#include <mach/mmp2.h>
#include <mach/irqs.h>
#include "common.h"
#define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40)
#define GPIO_5V_ENABLE (89)
static unsigned long brownstone_pin_config[] __initdata = {
/* UART1 */
GPIO29_UART1_RXD,
GPIO30_UART1_TXD,
/* UART3 */
GPIO51_UART3_RXD,
GPIO52_UART3_TXD,
/* DFI */
GPIO168_DFI_D0,
GPIO167_DFI_D1,
GPIO166_DFI_D2,
GPIO165_DFI_D3,
GPIO107_DFI_D4,
GPIO106_DFI_D5,
GPIO105_DFI_D6,
GPIO104_DFI_D7,
GPIO111_DFI_D8,
GPIO164_DFI_D9,
GPIO163_DFI_D10,
GPIO162_DFI_D11,
GPIO161_DFI_D12,
GPIO110_DFI_D13,
GPIO109_DFI_D14,
GPIO108_DFI_D15,
GPIO143_ND_nCS0,
GPIO144_ND_nCS1,
GPIO147_ND_nWE,
GPIO148_ND_nRE,
GPIO150_ND_ALE,
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC0 */
GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
GPIO136_MMC1_CMD | MFP_PULL_HIGH,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD | MFP_PULL_LOW,
GPIO141_MMC1_WP | MFP_PULL_LOW,
/* MMC1 */
GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
GPIO41_MMC2_CMD | MFP_PULL_HIGH,
GPIO42_MMC2_CLK,
/* MMC2 */
GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
GPIO112_MMC3_CMD | MFP_PULL_HIGH,
GPIO151_MMC3_CLK,
/* 5V regulator */
GPIO89_GPIO,
};
static struct regulator_consumer_supply max8649_supply[] = {
REGULATOR_SUPPLY("vcc_core", NULL),
};
static struct regulator_init_data max8649_init_data = {
.constraints = {
.name = "vcc_core range",
.min_uV = 1150000,
.max_uV = 1280000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max8649_supply[0],
};
static struct max8649_platform_data brownstone_max8649_info = {
.mode = 2, /* VID1 = 1, VID0 = 0 */
.extclk = 0,
.ramp_timing = MAX8649_RAMP_32MV,
.regulator = &max8649_init_data,
};
static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
REGULATOR_SUPPLY("v_5vp", NULL),
};
static struct regulator_init_data brownstone_v_5vp_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
.consumer_supplies = brownstone_v_5vp_supplies,
};
static struct fixed_voltage_config brownstone_v_5vp = {
.supply_name = "v_5vp",
.microvolts = 5000000,
.gpio = GPIO_5V_ENABLE,
.enable_high = 1,
.enabled_at_boot = 1,
.init_data = &brownstone_v_5vp_data,
};
static struct platform_device brownstone_v_5vp_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &brownstone_v_5vp,
},
};
static struct max8925_platform_data brownstone_max8925_info = {
.irq_base = IRQ_BOARD_START,
};
static struct i2c_board_info brownstone_twsi1_info[] = {
[0] = {
.type = "max8649",
.addr = 0x60,
.platform_data = &brownstone_max8649_info,
},
[1] = {
.type = "max8925",
.addr = 0x3c,
.irq = IRQ_MMP2_PMIC,
.platform_data = &brownstone_max8925_info,
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.max_speed = 25000000,
};
static void __init brownstone_init(void)
{
mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
/* enable 5v regulator */
platform_device_register(&brownstone_v_5vp_device);
}
MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
/* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
.map_io = mmp_map_io,
.nr_irqs = BROWNSTONE_NR_IRQS,
.init_irq = mmp2_init_irq,
.timer = &mmp2_timer,
.init_machine = brownstone_init,
MACHINE_END

2
arch/arm/mach-mmp/flint.c
View File

@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = {
GPIO113_SMC_RDY,
/*Ethernet*/
GPIO155_GPIO155,
GPIO155_GPIO,
/* DFI */
GPIO168_DFI_D0,

338
arch/arm/mach-mmp/include/mach/mfp-mmp2.h
View File

@ -9,175 +9,175 @@
#define MFP_DRIVE_FAST (0x8 << 13)
/* GPIO */
#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1)
#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1)
#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1)
#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1)
#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1)
#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1)
#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1)
#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1)
#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1)
#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1)
#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1)
#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1)
#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0)
#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0)
#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0)
#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0)
#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0)
#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0)
#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0)
#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0)
#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0)
#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0)
#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0)
#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0)
#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0)
#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0)
#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0)
#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1)
#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1)
#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1)
#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1)
#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1)
#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1)
#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1)
#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1)
#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1)
#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1)
#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1)
#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1)
#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1)
#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1)
#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1)
#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1)
#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1)
#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1)
#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1)
#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1)
#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1)
#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1)
#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1)
#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1)
#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1)
#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1)
#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1)
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
/* DFI */
#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)

22
arch/arm/mach-mmp/include/mach/mmp2.h
View File

@ -1,6 +1,8 @@
#ifndef __ASM_MACH_MMP2_H
#define __ASM_MACH_MMP2_H
#include <plat/sdhci.h>
struct sys_timer;
extern struct sys_timer mmp2_timer;
@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3;
extern struct pxa_device_desc mmp2_device_twsi4;
extern struct pxa_device_desc mmp2_device_twsi5;
extern struct pxa_device_desc mmp2_device_twsi6;
extern struct pxa_device_desc mmp2_device_sdh0;
extern struct pxa_device_desc mmp2_device_sdh1;
extern struct pxa_device_desc mmp2_device_sdh2;
extern struct pxa_device_desc mmp2_device_sdh3;
static inline int mmp2_add_uart(int id)
{
@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
return pxa_register_device(d, data, sizeof(*data));
}
static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
{
struct pxa_device_desc *d = NULL;
switch (id) {
case 0: d = &mmp2_device_sdh0; break;
case 1: d = &mmp2_device_sdh1; break;
case 2: d = &mmp2_device_sdh2; break;
case 3: d = &mmp2_device_sdh3; break;
default:
return -EINVAL;
}
return pxa_register_device(d, data, sizeof(*data));
}
#endif /* __ASM_MACH_MMP2_H */

2
arch/arm/mach-mmp/include/mach/regs-apmu.h
View File

@ -27,6 +27,8 @@
#define APMU_DMA APMU_REG(0x064)
#define APMU_GEU APMU_REG(0x068)
#define APMU_BUS APMU_REG(0x06c)
#define APMU_SDH2 APMU_REG(0x0e8)
#define APMU_SDH3 APMU_REG(0x0ec)
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)

35
arch/arm/mach-mmp/jasper.c
View File

@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = {
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC1 */
GPIO131_MMC1_DAT3,
GPIO132_MMC1_DAT2,
GPIO133_MMC1_DAT1,
GPIO134_MMC1_DAT0,
GPIO136_MMC1_CMD,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD,
GPIO141_MMC1_WP,
/* MMC2 */
GPIO37_MMC2_DAT3,
GPIO38_MMC2_DAT2,
GPIO39_MMC2_DAT1,
GPIO40_MMC2_DAT0,
GPIO41_MMC2_CMD,
GPIO42_MMC2_CLK,
/* MMC3 */
GPIO165_MMC3_DAT7,
GPIO162_MMC3_DAT6,
GPIO166_MMC3_DAT5,
GPIO163_MMC3_DAT4,
GPIO167_MMC3_DAT3,
GPIO164_MMC3_DAT2,
GPIO168_MMC3_DAT1,
GPIO111_MMC3_DAT0,
GPIO112_MMC3_CMD,
GPIO151_MMC3_CLK,
};
static struct regulator_consumer_supply max8649_supply[] = {
@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = {
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.max_speed = 25000000,
};
static void __init jasper_init(void)
{
mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
@ -131,6 +165,7 @@ static void __init jasper_init(void)
mmp2_add_uart(1);
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
regulator_has_full_constraints();
}

35
arch/arm/mach-mmp/mmp2.c
View File

@ -115,6 +115,29 @@ void __init mmp2_init_irq(void)
mmp2_init_gpio();
}
static void sdhc_clk_enable(struct clk *clk)
{
uint32_t clk_rst;
clk_rst = __raw_readl(clk->clk_rst);
clk_rst |= clk->enable_val;
__raw_writel(clk_rst, clk->clk_rst);
}
static void sdhc_clk_disable(struct clk *clk)
{
uint32_t clk_rst;
clk_rst = __raw_readl(clk->clk_rst);
clk_rst &= ~clk->enable_val;
__raw_writel(clk_rst, clk->clk_rst);
}
struct clkops sdhc_clk_ops = {
.enable = sdhc_clk_enable,
.disable = sdhc_clk_disable,
};
/* APB peripheral clocks */
static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
@ -128,6 +151,10 @@ static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
static APMU_CLK(nand, NAND, 0xbf, 100000000);
static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@ -141,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
};
static int __init mmp2_init(void)
@ -191,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);

2
arch/arm/mach-mmp/pxa910.c
View File

@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
static APMU_CLK(nand, NAND, 0x01db, 208000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */
static struct clk_lookup pxa910_clkregs[] = {
@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = {
INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
};
static int __init pxa910_init(void)

2
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
View File

@ -65,7 +65,7 @@
*/
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570)
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)

34
arch/arm/mach-mx25/Kconfig
View File

@ -1,34 +0,0 @@
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif

5
arch/arm/mach-mx25/Makefile
View File

@ -1,5 +0,0 @@
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o

3
arch/arm/mach-mx25/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

308
arch/arm/mach-mx25/devices.c
View File

@ -1,308 +0,0 @@
/*
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/mx25.h>
#include <mach/irqs.h>
static u64 otg_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_otg_resources[] = {
{
.start = MX25_OTG_BASE_ADDR,
.end = MX25_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = 37,
.end = 37,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_otg = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
/* OTG gadget device */
struct platform_device otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX25_OTG_BASE_ADDR + 0x400,
.end = MX25_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = 35,
.end = 35,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource mxc_pwm_resources0[] = {
{
.start = 0x53fe0000,
.end = 0x53fe3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 26,
.end = 26,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device0 = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources0),
.resource = mxc_pwm_resources0,
};
static struct resource mxc_pwm_resources1[] = {
{
.start = 0x53fa0000,
.end = 0x53fa3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 36,
.end = 36,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device1 = {
.name = "mxc_pwm",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_pwm_resources1),
.resource = mxc_pwm_resources1,
};
static struct resource mxc_pwm_resources2[] = {
{
.start = 0x53fa8000,
.end = 0x53fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 41,
.end = 41,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device2 = {
.name = "mxc_pwm",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_pwm_resources2),
.resource = mxc_pwm_resources2,
};
static struct resource mxc_keypad_resources[] = {
{
.start = 0x43fa8000,
.end = 0x43fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 24,
.end = 24,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_keypad_device = {
.name = "mxc-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mxc_keypad_resources),
.resource = mxc_keypad_resources,
};
static struct resource mxc_pwm_resources3[] = {
{
.start = 0x53fc8000,
.end = 0x53fcbfff,
.flags = IORESOURCE_MEM,
}, {
.start = 42,
.end = 42,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device3 = {
.name = "mxc_pwm",
.id = 3,
.num_resources = ARRAY_SIZE(mxc_pwm_resources3),
.resource = mxc_pwm_resources3,
};
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
.irq = 52,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
.irq = 51,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
.irq = 16,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
.irq = 23,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx25_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mx25_rtc_resources[] = {
{
.start = MX25_DRYICE_BASE_ADDR,
.end = MX25_DRYICE_BASE_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_DRYICE,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_rtc_device = {
.name = "imxdi_rtc",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_rtc_resources),
.resource = mx25_rtc_resources,
};
static struct resource mx25_fb_resources[] = {
{
.start = MX25_LCDC_BASE_ADDR,
.end = MX25_LCDC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_LCDC,
.end = MX25_INT_LCDC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_fb_device = {
.name = "imx-fb",
.id = 0,
.resource = mx25_fb_resources,
.num_resources = ARRAY_SIZE(mx25_fb_resources),
.dev = {
.coherent_dma_mask = 0xFFFFFFFF,
},
};
static struct resource mxc_wdt_resources[] = {
{
.start = MX25_WDOG_BASE_ADDR,
.end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mx25_kpp_resources[] = {
{
.start = MX25_KPP_BASE_ADDR,
.end = MX25_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_KPP,
.end = MX25_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mx25_kpp_resources),
.resource = mx25_kpp_resources,
};
static struct resource mx25_csi_resources[] = {
{
.start = MX25_CSI_BASE_ADDR,
.end = MX25_CSI_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_CSI,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_csi_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_csi_resources),
.resource = mx25_csi_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};

13
arch/arm/mach-mx25/devices.h
View File

@ -1,13 +0,0 @@
extern struct platform_device mxc_otg;
extern struct platform_device otg_udc_device;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_pwm_device0;
extern struct platform_device mxc_pwm_device1;
extern struct platform_device mxc_pwm_device2;
extern struct platform_device mxc_pwm_device3;
extern struct platform_device mxc_keypad_device;
extern struct platform_device mx25_rtc_device;
extern struct platform_device mx25_fb_device;
extern struct platform_device mxc_wdt;
extern struct platform_device mx25_kpp_device;
extern struct platform_device mx25_csi_device;

86
arch/arm/mach-mx3/Kconfig
View File

@ -1,21 +1,35 @@
if ARCH_MX3
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
select ARCH_HAS_RNGA
select ARCH_MXC_AUDMUX_V2
bool
config ARCH_MX35
bool
config SOC_IMX31
bool
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
comment "MX3 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
@ -57,9 +76,12 @@ config MACH_PCM037_EET
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select ARCH_MX31
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
@ -68,11 +90,16 @@ config MACH_MX31LITE
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select ARCH_MX31
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -99,8 +129,10 @@ config MACH_MX31MOBOARD
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
@ -109,7 +141,7 @@ config MACH_MX31LILLY
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
@ -117,13 +149,16 @@ config MACH_QONG
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
@ -131,9 +166,11 @@ config MACH_PCM043
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
default n
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select ARCH_MX35
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_MXC_NAND
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes

7
arch/arm/mach-mx3/Makefile
View File

@ -5,17 +5,14 @@
# Object file lists.
obj-y := mm.o devices.o cpu.o
CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_SOC_IMX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o

4
arch/arm/mach-mx3/clock-imx31.c
View File

@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
_REGISTER_CLOCK(NULL, "epit", epit1_clk)
_REGISTER_CLOCK(NULL, "epit", epit2_clk)
@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_read_cpu_rev();
if (mx31_revision() >= MX31_CHIP_REV_2_0) {
if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */
reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;

2
arch/arm/mach-mx3/clock-imx35.c
View File

@ -494,7 +494,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "max", max_clk)
_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
_REGISTER_CLOCK(NULL, "csi", csi_clk)

31
arch/arm/mach-mx3/cpu.c
View File

@ -25,15 +25,15 @@ struct mx3_cpu_type {
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
};
void __init mx31_read_cpu_rev(void)
@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void)
return;
}
mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}
@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev = "unknown";
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = MX3x_CHIP_REV_1_0;
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = MX3x_CHIP_REV_2_0;
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = MX3x_CHIP_REV_2_1;
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);

27
arch/arm/mach-mx3/devices-imx31.h
View File

@ -9,6 +9,14 @@
#include <mach/mx31.h>
#include <mach/devices-common.h>
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
#define imx31_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
#define imx31_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
#define imx31_add_cspi(id, pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)

41
arch/arm/mach-mx3/devices-imx35.h
View File

@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
#define imx35_add_flexcan0(pdata) \
imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
#define imx35_add_flexcan1(pdata) \
imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
#define imx35_add_flexcan(id, pdata) \
imx_add_flexcan(&imx35_flexcan_data[id], pdata)
#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
#define imx35_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c(id, pdata) \
@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
#define imx35_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst;
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
#define imx35_add_esdhc(id, pdata) \
imx_add_esdhc(&imx35_esdhc_data[id], pdata)

271
arch/arm/mach-mx3/devices.c
View File

@ -29,120 +29,25 @@
#include "devices.h"
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}
};
int __init imx3x_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mxc_w1_master_resources[] = {
{
.start = OWIRE_BASE_ADDR,
.end = OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
{
.start = MX31_MMC_SDHC1_BASE_ADDR,
.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC1,
.end = MX31_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxcsdhc1_resources[] = {
{
.start = MX31_MMC_SDHC2_BASE_ADDR,
.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC2,
.end = MX31_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxcsdhc_device0 = {
.name = "mxc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
.resource = mxcsdhc0_resources,
};
struct platform_device mxcsdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
.resource = mxcsdhc1_resources,
};
static struct resource rnga_resources[] = {
{
.start = RNGA_BASE_ADDR,
.end = RNGA_BASE_ADDR + 0x28,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_rnga_device = {
.name = "mxc_rnga",
.id = -1,
.num_resources = 1,
.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */
/* i.MX31 Image Processing Unit */
/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
{
.start = IPU_CTRL_BASE_ADDR,
.end = IPU_CTRL_BASE_ADDR + 0x5F,
.start = MX3x_IPU_CTRL_BASE_ADDR,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
.flags = IORESOURCE_MEM,
}, {
.start = IPU_CTRL_BASE_ADDR + 0x88,
.end = IPU_CTRL_BASE_ADDR + 0xB3,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_IPU_SYN,
.end = MXC_INT_IPU_SYN,
.start = MX3x_INT_IPU_SYN,
.end = MX3x_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC_INT_IPU_ERR,
.end = MXC_INT_IPU_ERR,
.start = MX3x_INT_IPU_ERR,
.end = MX3x_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
static struct resource fb_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0xB4,
.end = IPU_CTRL_BASE_ADDR + 0x1BF,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
.flags = IORESOURCE_MEM,
},
};
@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
static struct resource camera_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0x60,
.end = IPU_CTRL_BASE_ADDR + 0x87,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
.flags = IORESOURCE_MEM,
},
};
@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
},
};
static struct resource otg_resources[] = {
{
.start = MX31_OTG_BASE_ADDR,
.end = MX31_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB3,
.end = MXC_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = ~(u32)0;
static struct resource mxc_usbh1_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x200,
.end = MX31_OTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB1,
.end = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;
static struct resource mxc_usbh2_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x400,
.end = MX31_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB2,
.end = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource imx_wdt_resources[] = {
{
.flags = IORESOURCE_MEM,
},
};
struct platform_device imx_wdt_device0 = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
.resource = imx_wdt_resources,
};
static struct resource imx_rtc_resources[] = {
{
.start = MX31_RTC_BASE_ADDR,
@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
.num_resources = ARRAY_SIZE(imx_rtc_resources),
.resource = imx_rtc_resources,
};
static struct resource imx_kpp_resources[] = {
{
.start = MX3x_KPP_BASE_ADDR,
.end = MX3x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX3x_INT_KPP,
.end = MX3x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
static int __init mx3_devices_init(void)
{
#if defined(CONFIG_ARCH_MX31)
if (cpu_is_mx31()) {
imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
mxc_register_device(&mxc_rnga_device, NULL);
}
#endif
#if defined(CONFIG_ARCH_MX35)
if (cpu_is_mx35()) {
otg_resources[0].start = MX35_OTG_BASE_ADDR;
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
otg_resources[1].start = MXC_INT_USBOTG;
otg_resources[1].end = MXC_INT_USBOTG;
mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
}
#endif
return 0;
}
subsys_initcall(mx3_devices_init);

10
arch/arm/mach-mx3/devices.h
View File

@ -1,14 +1,4 @@
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mx3_ipu;
extern struct platform_device mx3_fb;
extern struct platform_device mx3_camera;
extern struct platform_device mxcsdhc_device0;
extern struct platform_device mxcsdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_rnga_device;
extern struct platform_device imx_wdt_device0;
extern struct platform_device imx_rtc_device0;
extern struct platform_device imx_kpp_device;

4
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View File

@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = {
.num_modes = ARRAY_SIZE(fb_modedb),
};
static struct pad_desc eukrea_mbimxsd_pads[] = {
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
MX35_PAD_LD0__IPU_DISPB_DAT_0,
MX35_PAD_LD1__IPU_DISPB_DAT_1,
@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);

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