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net/mlx5e: Fix endianness handling in pedit mask

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The mask value is provided as 64 bit and has to be casted in
either 32 or 16 bit. On big endian systems the wrong half was
casted which resulted in an all zero mask.

Fixes: 2b64beba02 ("net/mlx5e: Support header re-write of partial fields in TC pedit offload")
Signed-off-by: Sebastian Hense <sebastian.hense1@ibm.com>
Reviewed-by: Roi Dayan <roid@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Sebastian Hense 2020-02-20 08:11:36 +01:00 committed by Saeed Mahameed
parent f28ca65efa
commit 404402abd5
1 changed files with 3 additions and 2 deletions
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5
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
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@ -2476,10 +2476,11 @@ static int offload_pedit_fields(struct pedit_headers_action *hdrs,
continue;
if (f->field_bsize == 32) {
mask_be32 = *(__be32 *)&mask;
mask_be32 = (__be32)mask;
mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
} else if (f->field_bsize == 16) {
mask_be16 = *(__be16 *)&mask;
mask_be32 = (__be32)mask;
mask_be16 = *(__be16 *)&mask_be32;
mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
}