forked from Minki/linux
irqchip: Add RZ/G2L IA55 Interrupt Controller driver
Add a driver for the Renesas RZ/G2L Interrupt Controller. This supports external pins being used as interrupts. It supports one line for NMI, 8 external pins and 32 GPIO pins (out of 123) to be used as IRQ lines. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220707182314.66610-4-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar
Marc Zyngier
parent
96fed779d3
commit
3fed09559c
@ -242,6 +242,14 @@ config RENESAS_RZA1_IRQC
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Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
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to 8 external interrupts with configurable sense select.
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config RENESAS_RZG2L_IRQC
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bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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help
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Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
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for external devices.
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config SL28CPLD_INTC
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bool "Kontron sl28cpld IRQ controller"
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depends on MFD_SL28CPLD=y || COMPILE_TEST
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@ -51,6 +51,7 @@ obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
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obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
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obj-$(CONFIG_RENESAS_RZG2L_IRQC) += irq-renesas-rzg2l.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
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obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
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393
drivers/irqchip/irq-renesas-rzg2l.c
Normal file
393
drivers/irqchip/irq-renesas-rzg2l.c
Normal file
@ -0,0 +1,393 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L IRQC Driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation.
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*
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* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#define IRQC_IRQ_START 1
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#define IRQC_IRQ_COUNT 8
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#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
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#define IRQC_TINT_COUNT 32
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#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
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#define ISCR 0x10
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#define IITSR 0x14
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#define TSCR 0x20
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#define TITSR0 0x24
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#define TITSR1 0x28
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#define TITSR0_MAX_INT 16
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#define TITSEL_WIDTH 0x2
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#define TSSR(n) (0x30 + ((n) * 4))
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#define TIEN BIT(7)
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#define TSSEL_SHIFT(n) (8 * (n))
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#define TSSEL_MASK GENMASK(7, 0)
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#define IRQ_MASK 0x3
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#define TSSR_OFFSET(n) ((n) % 4)
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#define TSSR_INDEX(n) ((n) / 4)
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#define TITSR_TITSEL_EDGE_RISING 0
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#define TITSR_TITSEL_EDGE_FALLING 1
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#define TITSR_TITSEL_LEVEL_HIGH 2
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#define TITSR_TITSEL_LEVEL_LOW 3
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#define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2))
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#define IITSR_IITSEL_LEVEL_LOW 0
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#define IITSR_IITSEL_EDGE_FALLING 1
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#define IITSR_IITSEL_EDGE_RISING 2
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#define IITSR_IITSEL_EDGE_BOTH 3
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#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
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#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
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#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
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struct rzg2l_irqc_priv {
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void __iomem *base;
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struct irq_fwspec fwspec[IRQC_NUM_IRQ];
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raw_spinlock_t lock;
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};
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static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
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{
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return data->domain->host_data;
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}
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static void rzg2l_irq_eoi(struct irq_data *d)
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{
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unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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u32 bit = BIT(hw_irq);
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u32 reg;
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reg = readl_relaxed(priv->base + ISCR);
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if (reg & bit)
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writel_relaxed(reg & ~bit, priv->base + ISCR);
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}
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static void rzg2l_tint_eoi(struct irq_data *d)
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{
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unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START;
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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u32 bit = BIT(hw_irq);
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u32 reg;
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reg = readl_relaxed(priv->base + TSCR);
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if (reg & bit)
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writel_relaxed(reg & ~bit, priv->base + TSCR);
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}
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static void rzg2l_irqc_eoi(struct irq_data *d)
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{
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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unsigned int hw_irq = irqd_to_hwirq(d);
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raw_spin_lock(&priv->lock);
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if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
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rzg2l_irq_eoi(d);
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else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
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rzg2l_tint_eoi(d);
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raw_spin_unlock(&priv->lock);
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irq_chip_eoi_parent(d);
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}
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static void rzg2l_irqc_irq_disable(struct irq_data *d)
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{
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unsigned int hw_irq = irqd_to_hwirq(d);
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if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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u32 offset = hw_irq - IRQC_TINT_START;
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u32 tssr_offset = TSSR_OFFSET(offset);
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u8 tssr_index = TSSR_INDEX(offset);
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u32 reg;
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raw_spin_lock(&priv->lock);
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reg = readl_relaxed(priv->base + TSSR(tssr_index));
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reg &= ~(TSSEL_MASK << tssr_offset);
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writel_relaxed(reg, priv->base + TSSR(tssr_index));
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raw_spin_unlock(&priv->lock);
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}
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irq_chip_disable_parent(d);
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}
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static void rzg2l_irqc_irq_enable(struct irq_data *d)
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{
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unsigned int hw_irq = irqd_to_hwirq(d);
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if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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unsigned long tint = (uintptr_t)d->chip_data;
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u32 offset = hw_irq - IRQC_TINT_START;
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u32 tssr_offset = TSSR_OFFSET(offset);
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u8 tssr_index = TSSR_INDEX(offset);
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u32 reg;
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raw_spin_lock(&priv->lock);
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reg = readl_relaxed(priv->base + TSSR(tssr_index));
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reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
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writel_relaxed(reg, priv->base + TSSR(tssr_index));
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raw_spin_unlock(&priv->lock);
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}
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irq_chip_enable_parent(d);
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}
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static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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u16 sense, tmp;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_LEVEL_LOW:
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sense = IITSR_IITSEL_LEVEL_LOW;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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sense = IITSR_IITSEL_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_RISING:
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sense = IITSR_IITSEL_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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sense = IITSR_IITSEL_EDGE_BOTH;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock(&priv->lock);
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tmp = readl_relaxed(priv->base + IITSR);
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tmp &= ~IITSR_IITSEL_MASK(hw_irq);
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tmp |= IITSR_IITSEL(hw_irq, sense);
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writel_relaxed(tmp, priv->base + IITSR);
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raw_spin_unlock(&priv->lock);
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return 0;
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}
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static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
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{
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struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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u32 titseln = hwirq - IRQC_TINT_START;
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u32 offset;
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u8 sense;
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u32 reg;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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sense = TITSR_TITSEL_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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sense = TITSR_TITSEL_EDGE_FALLING;
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break;
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default:
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return -EINVAL;
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}
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offset = TITSR0;
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if (titseln >= TITSR0_MAX_INT) {
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titseln -= TITSR0_MAX_INT;
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offset = TITSR1;
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}
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raw_spin_lock(&priv->lock);
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reg = readl_relaxed(priv->base + offset);
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reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
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reg |= sense << (titseln * TITSEL_WIDTH);
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writel_relaxed(reg, priv->base + offset);
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raw_spin_unlock(&priv->lock);
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return 0;
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}
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static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int hw_irq = irqd_to_hwirq(d);
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int ret = -EINVAL;
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if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
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ret = rzg2l_irq_set_type(d, type);
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else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
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ret = rzg2l_tint_set_edge(d, type);
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if (ret)
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return ret;
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static const struct irq_chip irqc_chip = {
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.name = "rzg2l-irqc",
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.irq_eoi = rzg2l_irqc_eoi,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_disable = rzg2l_irqc_irq_disable,
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.irq_enable = rzg2l_irqc_irq_enable,
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.irq_get_irqchip_state = irq_chip_get_parent_state,
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.irq_set_irqchip_state = irq_chip_set_parent_state,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = rzg2l_irqc_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE,
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};
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static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct rzg2l_irqc_priv *priv = domain->host_data;
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unsigned long tint = 0;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
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if (ret)
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return ret;
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/*
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* For TINT interrupts ie where pinctrl driver is child of irqc domain
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* the hwirq and TINT are encoded in fwspec->param[0].
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* hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
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* from 16-31 bits. TINT from the pinctrl driver needs to be programmed
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* in IRQC registers to enable a given gpio pin as interrupt.
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*/
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if (hwirq > IRQC_IRQ_COUNT) {
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tint = TINT_EXTRACT_GPIOINT(hwirq);
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hwirq = TINT_EXTRACT_HWIRQ(hwirq);
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if (hwirq < IRQC_TINT_START)
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return -EINVAL;
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}
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if (hwirq > (IRQC_NUM_IRQ - 1))
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return -EINVAL;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
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(void *)(uintptr_t)tint);
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if (ret)
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return ret;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
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}
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static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
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.alloc = rzg2l_irqc_alloc,
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.free = irq_domain_free_irqs_common,
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.translate = irq_domain_translate_twocell,
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};
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static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
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struct device_node *np)
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{
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struct of_phandle_args map;
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unsigned int i;
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int ret;
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for (i = 0; i < IRQC_NUM_IRQ; i++) {
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ret = of_irq_parse_one(np, i, &map);
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if (ret)
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return ret;
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of_phandle_args_to_fwspec(np, map.args, map.args_count,
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&priv->fwspec[i]);
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}
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return 0;
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}
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static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *irq_domain, *parent_domain;
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struct platform_device *pdev;
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struct reset_control *resetn;
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struct rzg2l_irqc_priv *priv;
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int ret;
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pdev = of_find_device_by_node(node);
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if (!pdev)
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return -ENODEV;
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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dev_err(&pdev->dev, "cannot find parent domain\n");
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return -ENODEV;
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}
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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ret = rzg2l_irqc_parse_interrupts(priv, node);
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if (ret) {
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dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
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return ret;
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}
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resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(resetn))
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return PTR_ERR(resetn);
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ret = reset_control_deassert(resetn);
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if (ret) {
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dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
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return ret;
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}
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pm_runtime_enable(&pdev->dev);
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ret = pm_runtime_resume_and_get(&pdev->dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
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goto pm_disable;
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}
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raw_spin_lock_init(&priv->lock);
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irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
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node, &rzg2l_irqc_domain_ops,
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priv);
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if (!irq_domain) {
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dev_err(&pdev->dev, "failed to add irq domain\n");
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ret = -ENOMEM;
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goto pm_put;
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}
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return 0;
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pm_put:
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pm_runtime_put(&pdev->dev);
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pm_disable:
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pm_runtime_disable(&pdev->dev);
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reset_control_assert(resetn);
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return ret;
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
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IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
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IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
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||||
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user