diff --git a/Documentation/devicetree/bindings/mips/loongson/ls2k-reset.yaml b/Documentation/devicetree/bindings/mips/loongson/ls2k-reset.yaml
new file mode 100644
index 000000000000..20b5836efd90
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/ls2k-reset.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson 2K1000 PM Controller
+
+maintainers:
+ - Qing Zhang <zhangqing@loongson.cn>
+
+description: |
+ This controller can be found in Loongson-2K1000 Soc systems.
+
+properties:
+ compatible:
+ const: loongson,ls2k-pm
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pm: reset-controller@1fe07000 {
+ compatible = "loongson,ls2k-pm";
+ reg = <0 0x1fe07000 0 0x422>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7c24d711b377..bc1dcb483dbb 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -19,6 +19,8 @@ properties:
- brcm,bcm7278-pcie # Broadcom 7278 Arm
- brcm,bcm7216-pcie # Broadcom 7216 Arm
- brcm,bcm7445-pcie # Broadcom 7445 Arm
+ - brcm,bcm7425-pcie # Broadcom 7425 MIPs
+ - brcm,bcm7435-pcie # Broadcom 7435 MIPs
reg:
maxItems: 1
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0215dc1529e9..3dd8c4618293 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -264,7 +264,6 @@ config BMIPS_GENERIC
bool "Broadcom Generic BMIPS kernel"
select ARCH_HAS_RESET_CONTROLLER
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
- select ARCH_HAS_PHYS_TO_DMA
select BOOT_RAW
select NO_EXCEPT_FILL
select USE_OF
@@ -640,9 +639,6 @@ config MACH_REALTEK_RTL
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_VPE_LOADER
- select SYS_HAS_EARLY_PRINTK
- select SYS_HAS_EARLY_PRINTK_8250
- select USE_GENERIC_EARLY_PRINTK_8250
select BOOT_RAW
select PINCTRL
select USE_OF
@@ -765,7 +761,6 @@ config SGI_IP30
select HAVE_PCI
select IRQ_MIPS_CPU
select IRQ_DOMAIN_HIERARCHY
- select NR_CPUS_DEFAULT_2
select PCI_DRIVERS_GENERIC
select PCI_XTALK_BRIDGE
select SYS_HAS_EARLY_PRINTK
@@ -1611,7 +1606,6 @@ config CPU_R4300
depends on SYS_HAS_CPU_R4300
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
- select CPU_HAS_LOAD_STORE_LR
help
MIPS Technologies R4300-series processors.
@@ -1907,6 +1901,10 @@ config SYS_HAS_CPU_MIPS64_R1
config SYS_HAS_CPU_MIPS64_R2
bool
+config SYS_HAS_CPU_MIPS64_R5
+ bool
+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
+
config SYS_HAS_CPU_MIPS64_R6
bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
@@ -2065,7 +2063,7 @@ config CPU_SUPPORTS_ADDRWINCFG
bool
config CPU_SUPPORTS_HUGEPAGES
bool
- depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
+ depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
config MIPS_PGD_C0_CONTEXT
bool
depends on 64BIT
@@ -2116,6 +2114,16 @@ config MIPS_VA_BITS_48
If unsure, say N.
+config ZBOOT_LOAD_ADDRESS
+ hex "Compressed kernel load address"
+ default 0xffffffff80400000 if BCM47XX
+ default 0x0
+ depends on SYS_SUPPORTS_ZBOOT
+ help
+ The address to load compressed kernel, aka vmlinuz.
+
+ This is only used if non-zero.
+
choice
prompt "Kernel page size"
default PAGE_SIZE_4KB
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index ace7f033de07..e036fc025ccc 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -253,9 +253,7 @@ endif
#
# Board-dependent options and extra files
#
-ifdef need-compiler
include $(srctree)/arch/mips/Kbuild.platforms
-endif
ifdef CONFIG_PHYSICAL_START
load-y = $(CONFIG_PHYSICAL_START)
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 7d5da5edd74d..a17d7a8909c4 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -23,8 +23,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Notes :
- * This file must ONLY be built when CONFIG_GPIOLIB=y and
- * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
* au1000 SoC have only one GPIO block : GPIO1
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
* Au1300 is totally different: 1 block with up to 128 GPIOs
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 891f495c4c3c..0ac435fe2dc9 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -34,15 +34,6 @@
static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
-static void ath79_restart(char *command)
-{
- local_irq_disable();
- ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
- for (;;)
- if (cpu_wait)
- cpu_wait();
-}
-
static void ath79_halt(void)
{
while (1)
@@ -234,7 +225,6 @@ void __init plat_mem_setup(void)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
- _machine_restart = ath79_restart;
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
diff --git a/arch/mips/bcm47xx/Platform b/arch/mips/bcm47xx/Platform
index 833b204fe5da..fe6daba3f948 100644
--- a/arch/mips/bcm47xx/Platform
+++ b/arch/mips/bcm47xx/Platform
@@ -4,4 +4,3 @@
cflags-$(CONFIG_BCM47XX) += \
-I$(srctree)/arch/mips/include/asm/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
-zload-$(CONFIG_BCM47XX) += 0xffffffff80400000
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index 35266a70e22a..87dc76a1f941 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
{{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
{{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
+ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
@@ -161,9 +162,12 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
{{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
{{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
@@ -345,7 +349,7 @@ void __init bcm47xx_board_detect(void)
board_detected = bcm47xx_board_get_nvram();
bcm47xx_board.board = board_detected->board;
- strlcpy(bcm47xx_board.name, board_detected->name,
+ strscpy(bcm47xx_board.name, board_detected->name,
BCM47XX_BOARD_MAX_NAME);
}
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
index 535d84addcdb..36f0b1aafaa2 100644
--- a/arch/mips/bcm47xx/buttons.c
+++ b/arch/mips/bcm47xx/buttons.c
@@ -26,6 +26,12 @@
/* Asus */
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_rtn10u[] __initconst = {
+ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON),
+ BCM47XX_GPIO_KEY(21, KEY_RESTART),
+};
+
static const struct gpio_keys_button
bcm47xx_buttons_asus_rtn12[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
@@ -276,6 +282,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __initconst = {
BCM47XX_GPIO_KEY(8, KEY_UNKNOWN),
};
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {
+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {
+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
+};
+
static const struct gpio_keys_button
bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
BCM47XX_GPIO_KEY(5, KEY_WIMAX),
@@ -391,6 +409,17 @@ bcm47xx_buttons_netgear_r6200_v1[] __initconst = {
BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
};
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_r6300_v1[] __initconst = {
+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = {
+ BCM47XX_GPIO_KEY(12, KEY_RESTART),
+ BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON),
+};
+
static const struct gpio_keys_button
bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
BCM47XX_GPIO_KEY(4, KEY_RESTART),
@@ -478,6 +507,9 @@ int __init bcm47xx_buttons_register(void)
int err;
switch (board) {
+ case BCM47XX_BOARD_ASUS_RTN10U:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u);
+ break;
case BCM47XX_BOARD_ASUS_RTN12:
err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
break;
@@ -608,6 +640,12 @@ int __init bcm47xx_buttons_register(void)
case BCM47XX_BOARD_LINKSYS_WRT310NV1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
break;
+ case BCM47XX_BOARD_LINKSYS_WRT310NV2:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
+ break;
+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);
+ break;
case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
break;
@@ -674,6 +712,12 @@ int __init bcm47xx_buttons_register(void)
case BCM47XX_BOARD_NETGEAR_R6200_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);
break;
+ case BCM47XX_BOARD_NETGEAR_R6300_V1:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
+ break;
+ case BCM47XX_BOARD_NETGEAR_WN2500RP_V1:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1);
+ break;
case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
break;
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
index 167c42c71e79..4648a302a3c0 100644
--- a/arch/mips/bcm47xx/leds.c
+++ b/arch/mips/bcm47xx/leds.c
@@ -29,6 +29,14 @@
/* Asus */
+static const struct gpio_led
+bcm47xx_leds_asus_rtn10u[] __initconst = {
+ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
+ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
static const struct gpio_led
bcm47xx_leds_asus_rtn12[] __initconst = {
BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
@@ -313,6 +321,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initconst = {
BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
};
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {
+ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
static const struct gpio_led
bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
@@ -556,6 +571,9 @@ void __init bcm47xx_leds_register(void)
enum bcm47xx_board board = bcm47xx_board_get();
switch (board) {
+ case BCM47XX_BOARD_ASUS_RTN10U:
+ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u);
+ break;
case BCM47XX_BOARD_ASUS_RTN12:
bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
break;
@@ -689,6 +707,9 @@ void __init bcm47xx_leds_register(void)
case BCM47XX_BOARD_LINKSYS_WRT310NV1:
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
break;
+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);
+ break;
case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
break;
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 1c91064cb448..6e6756e8fa0a 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -387,6 +387,12 @@ struct clk *clk_get_parent(struct clk *clk)
}
EXPORT_SYMBOL(clk_get_parent);
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index 915ce4b189c1..c535f9cb75ec 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -1,68 +1,8 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
- */
+// SPDX-License-Identifier: GPL-2.0+
-#define pr_fmt(fmt) "bmips-dma: " fmt
-
-#include <linux/device.h>
-#include <linux/dma-direction.h>
-#include <linux/dma-direct.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/printk.h>
-#include <linux/slab.h>
#include <linux/types.h>
#include <asm/bmips.h>
-
-/*
- * BCM338x has configurable address translation windows which allow the
- * peripherals' DMA addresses to be different from the Zephyr-visible
- * physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
- *
- * If the "brcm,ubus" node has a "dma-ranges" property we will enable this
- * translation globally using the provided information. This implements a
- * very limited subset of "dma-ranges" support and it will probably be
- * replaced by a more generic version later.
- */
-
-struct bmips_dma_range {
- u32 child_addr;
- u32 parent_addr;
- u32 size;
-};
-
-static struct bmips_dma_range *bmips_dma_ranges;
-
-#define FLUSH_RAC 0x100
-
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t pa)
-{
- struct bmips_dma_range *r;
-
- for (r = bmips_dma_ranges; r && r->size; r++) {
- if (pa >= r->child_addr &&
- pa < (r->child_addr + r->size))
- return pa - r->child_addr + r->parent_addr;
- }
- return pa;
-}
-
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
-{
- struct bmips_dma_range *r;
-
- for (r = bmips_dma_ranges; r && r->size; r++) {
- if (dma_addr >= r->parent_addr &&
- dma_addr < (r->parent_addr + r->size))
- return dma_addr - r->parent_addr + r->child_addr;
- }
- return dma_addr;
-}
+#include <asm/io.h>
void arch_sync_dma_for_cpu_all(void)
{
@@ -79,45 +19,3 @@ void arch_sync_dma_for_cpu_all(void)
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
}
-
-static int __init bmips_init_dma_ranges(void)
-{
- struct device_node *np =
- of_find_compatible_node(NULL, NULL, "brcm,ubus");
- const __be32 *data;
- struct bmips_dma_range *r;
- int len;
-
- if (!np)
- return 0;
-
- data = of_get_property(np, "dma-ranges", &len);
- if (!data)
- goto out_good;
-
- len /= sizeof(*data) * 3;
- if (!len)
- goto out_bad;
-
- /* add a dummy (zero) entry at the end as a sentinel */
- bmips_dma_ranges = kcalloc(len + 1, sizeof(struct bmips_dma_range),
- GFP_KERNEL);
- if (!bmips_dma_ranges)
- goto out_bad;
-
- for (r = bmips_dma_ranges; len; len--, r++) {
- r->child_addr = be32_to_cpup(data++);
- r->parent_addr = be32_to_cpup(data++);
- r->size = be32_to_cpup(data++);
- }
-
-out_good:
- of_node_put(np);
- return 0;
-
-out_bad:
- pr_err("error parsing dma-ranges property\n");
- of_node_put(np);
- return -EINVAL;
-}
-arch_initcall(bmips_init_dma_ranges);
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index f27cf31b4140..8b03ef13133a 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -52,7 +52,7 @@ endif
vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o
-vmlinuzobjs-$(CONFIG_KERNEL_ZSTD) += $(obj)/bswapdi.o $(obj)/ashldi3.o
+vmlinuzobjs-$(CONFIG_KERNEL_ZSTD) += $(obj)/bswapdi.o $(obj)/ashldi3.o $(obj)/clz_ctz.o
targets := $(notdir $(vmlinuzobjs-y))
@@ -89,6 +89,10 @@ HOSTCFLAGS_calc_vmlinuz_load_addr.o += $(LINUXINCLUDE)
# Calculate the load address of the compressed kernel image
hostprogs := calc_vmlinuz_load_addr
+ifneq (0x0,$(CONFIG_ZBOOT_LOAD_ADDRESS))
+zload-y = $(CONFIG_ZBOOT_LOAD_ADDRESS)
+endif
+
ifneq ($(zload-y),)
VMLINUZ_LOAD_ADDRESS := $(zload-y)
else
diff --git a/arch/mips/boot/compressed/clz_ctz.c b/arch/mips/boot/compressed/clz_ctz.c
new file mode 100644
index 000000000000..b4a1b6eb2f8a
--- /dev/null
+++ b/arch/mips/boot/compressed/clz_ctz.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "../../../../lib/clz_ctz.c"
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index aa0b2d39c902..62588c53d356 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -584,4 +584,34 @@
};
};
};
+
+ pcie_0: pcie@8b20000 {
+ status = "disabled";
+ compatible = "brcm,bcm7425-pcie";
+
+ ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
+ 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
+ 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
+ 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
+
+ reg = <0x10410000 0x19310>;
+ aspm-no-l0s;
+ device_type = "pci";
+ msi-controller;
+ msi-parent = <&pcie_0>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ linux,pci-domain = <0x0>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <37>, <37>;
+ interrupt-names = "pcie", "msi";
+ #interrupt-cells = <0x1>;
+ interrupt-map = <0 0 0 1 &periph_intc 0x21
+ 0 0 0 1 &periph_intc 0x22
+ 0 0 0 1 &periph_intc 0x23
+ 0 0 0 1 &periph_intc 0x24>;
+ };
};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 8398b7f68bf4..8c001b944c8b 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -599,4 +599,34 @@
};
};
};
+
+ pcie_0: pcie@8b20000 {
+ status = "disabled";
+ compatible = "brcm,bcm7435-pcie";
+
+ ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
+ 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
+ 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
+ 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
+
+ reg = <0x10410000 0x19310>;
+ aspm-no-l0s;
+ device_type = "pci";
+ msi-controller;
+ msi-parent = <&pcie_0>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ linux,pci-domain = <0x0>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <39>, <39>;
+ interrupt-names = "pcie", "msi";
+ #interrupt-cells = <0x1>;
+ interrupt-map = <0 0 0 1 &periph_intc 0x23
+ 0 0 0 1 &periph_intc 0x24
+ 0 0 0 1 &periph_intc 0x25
+ 0 0 0 1 &periph_intc 0x26>;
+ };
};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 9efecfe1e05c..f38934934349 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -152,3 +152,12 @@
&waketimer {
status = "okay";
};
+
+&pcie_0 {
+ status = "okay";
+ /* 1GB Memc0, 1GB Memc1 */
+ brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
+ dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
+ 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
+ 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index b653c6ff74b5..a0cf53e23c07 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -128,3 +128,12 @@
&waketimer {
status = "okay";
};
+
+&pcie_0 {
+ status = "okay";
+ /* 1GB Memc0, 1GB Memc1 */
+ brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
+ dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
+ 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
+ 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
+};
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index b249a4f0f6b6..3e336b3dbb10 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -78,6 +78,18 @@
enable-active-high;
};
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&dw_hdmi_out>;
+ };
+ };
+ };
+
ir: ir {
compatible = "gpio-ir-receiver";
gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
@@ -102,6 +114,17 @@
gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
enable-active-high;
};
+
+ hdmi_power: fixedregulator@3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpa 25 0>;
+ enable-active-high;
+ };
};
&ext {
@@ -114,11 +137,12 @@
* precision.
*/
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
- <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>;
+ <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
+ <&cgu JZ4780_CLK_HDMI>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
<&cgu JZ4780_CLK_MPLL>,
<&cgu JZ4780_CLK_SSIPLL>;
- assigned-clock-rates = <48000000>, <0>, <54000000>;
+ assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
};
&tcu {
@@ -509,6 +533,12 @@
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
@@ -539,3 +569,41 @@
bias-disable;
};
};
+
+&hdmi {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_hdmi_ddc>;
+
+ hdmi-5v-supply = <&hdmi_power>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <&lcd_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+};
+
+&lcdc0 {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <&dw_hdmi_in>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
index 0c6a5a4266f4..e9e48022f631 100644
--- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
@@ -321,7 +321,7 @@
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4725b-lcd";
- reg = <0x13050000 0x1000>;
+ reg = <0x13050000 0x130>; /* tbc */
interrupt-parent = <&intc>;
interrupts = <31>;
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 772542e1f266..7f76cba03a08 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -323,7 +323,7 @@
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4740-lcd";
- reg = <0x13050000 0x1000>;
+ reg = <0x13050000 0x60>; /* LCDCMD1+4 */
interrupt-parent = <&intc>;
interrupts = <30>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index dfe74328ae5d..bda0a3a86ed5 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -399,7 +399,7 @@
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4770-lcd";
- reg = <0x13050000 0x300>;
+ reg = <0x13050000 0x130>; /* tbc */
interrupt-parent = <&intc>;
interrupts = <31>;
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b0a4e2e019c3..3f9ea47a10cd 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -444,6 +444,46 @@
status = "disabled";
};
+ hdmi: hdmi@10180000 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x10180000 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+
+ interrupt-parent = <&intc>;
+ interrupts = <3>;
+
+ status = "disabled";
+ };
+
+ lcdc0: lcdc0@13050000 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x13050000 0x1800>;
+
+ clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
+ lcdc1: lcdc1@130a0000 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x130a0000 0x1800>;
+
+ clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <&intc>;
+ interrupts = <23>;
+
+ status = "disabled";
+ };
+
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc", "simple-mfd";
reg = <0x13410000 0x10000>;
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index bfc3d3243ee7..8143a61111e3 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -52,6 +52,11 @@
0 0x40000000 0 0x40000000 0 0x40000000
0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+ pm: reset-controller@1fe07000 {
+ compatible = "loongson,ls2k-pm";
+ reg = <0 0x1fe07000 0 0x422>;
+ };
+
liointc0: interrupt-controller@1fe11400 {
compatible = "loongson,liointc-2.0";
reg = <0 0x1fe11400 0 0x40>,
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index d56e9b9d2e43..a994022e32c9 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -328,6 +328,7 @@ static int __init octeon_ehci_device_init(void)
pd->dev.platform_data = &octeon_ehci_pdata;
octeon_ehci_hw_start(&pd->dev);
+ put_device(&pd->dev);
return ret;
}
@@ -391,6 +392,7 @@ static int __init octeon_ohci_device_init(void)
pd->dev.platform_data = &octeon_ohci_pdata;
octeon_ohci_hw_start(&pd->dev);
+ put_device(&pd->dev);
return ret;
}
diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c
index 6e4d3619137a..4df919d26b08 100644
--- a/arch/mips/cavium-octeon/octeon-usb.c
+++ b/arch/mips/cavium-octeon/octeon-usb.c
@@ -537,6 +537,7 @@ static int __init dwc3_octeon_device_init(void)
devm_iounmap(&pdev->dev, base);
devm_release_mem_region(&pdev->dev, res->start,
resource_size(res));
+ put_device(&pdev->dev);
}
} while (node != NULL);
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index ab7ebb066834..cc69b215854e 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -98,7 +98,13 @@ CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_MEDIA_SUPPORT=m
+CONFIG_DRM=m
+CONFIG_DRM_INGENIC=m
+CONFIG_DRM_INGENIC_DW_HDMI=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_VGA_CONSOLE is not set
+CONFIG_FB=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_HID is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 69f2300107f9..f8212a813be7 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -10,9 +10,6 @@ CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MACH_TX49XX=y
CONFIG_TOSHIBA_RBTX4927=y
-CONFIG_TOSHIBA_RBTX4938=y
-CONFIG_TOSHIBA_RBTX4939=y
-CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y
# CONFIG_SECCOMP is not set
CONFIG_PCI=y
CONFIG_MODULES=y
@@ -38,7 +35,6 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RBTX4939=y
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_TXX9NDFMC=m
CONFIG_BLK_DEV_LOOP=y
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index cc988bbd27fc..cb12eb211a49 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -113,7 +113,7 @@ void __init prom_init(void)
if ((current_cpu_type() == CPU_R4000SC) ||
(current_cpu_type() == CPU_R4400SC)) {
static const char r4k_msg[] __initconst =
- "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
+ "Please recompile with \"CONFIG_CPU_R4X00 = y\".\n";
printk(cpu_msg);
printk(r4k_msg);
dec_machine_halt();
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index e1abc113b409..0c03623f3897 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -13,8 +13,7 @@ cflags-$(CONFIG_MACH_INGENIC_SOC) += -I$(srctree)/arch/mips/include/asm/mach-ing
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
-zload-$(CONFIG_MIPS_GENERIC) += 0xffffffff81000000
-all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
+all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
its-y := vmlinux.its.S
its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c
index 1842cddd8356..1d712eac1617 100644
--- a/arch/mips/generic/init.c
+++ b/arch/mips/generic/init.c
@@ -110,14 +110,15 @@ void __init plat_mem_setup(void)
void __init device_tree_init(void)
{
- int err;
-
unflatten_and_copy_device_tree();
mips_cpc_probe();
- err = register_cps_smp_ops();
- if (err)
- err = register_up_smp_ops();
+ if (!register_cps_smp_ops())
+ return;
+ if (!register_vsmp_smp_ops())
+ return;
+
+ register_up_smp_ops();
}
int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 2f8ce94ebaaf..6ffdd4b5e1d0 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -19,6 +19,7 @@
#include <asm/sgidefs.h>
#include <asm/asm-eva.h>
+#include <asm/isa-rev.h>
#ifndef __VDSO__
/*
@@ -211,6 +212,8 @@ symbol = value
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
+#define LONG_LL ll
+#define LONG_SC sc
#define LONG_S sw
#define LONG_SP swp
#define LONG_SLL sll
@@ -219,6 +222,8 @@ symbol = value
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
+#define LONG_INS ins
+#define LONG_EXT ext
#ifdef __ASSEMBLY__
#define LONG .word
@@ -236,6 +241,8 @@ symbol = value
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
+#define LONG_LL lld
+#define LONG_SC scd
#define LONG_S sd
#define LONG_SP sdp
#define LONG_SLL dsll
@@ -244,6 +251,8 @@ symbol = value
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
+#define LONG_INS dins
+#define LONG_EXT dext
#ifdef __ASSEMBLY__
#define LONG .dword
@@ -320,6 +329,19 @@ symbol = value
#define SSNOP sll zero, zero, 1
+/*
+ * Using a branch-likely instruction to check the result of an sc instruction
+ * works around a bug present in R10000 CPUs prior to revision 3.0 that could
+ * cause ll-sc sequences to execute non-atomically.
+ */
+#ifdef CONFIG_WAR_R10000_LLSC
+# define SC_BEQZ beqzl
+#elif MIPS_ISA_REV >= 6
+# define SC_BEQZ beqzc
+#else
+# define SC_BEQZ beqz
+#endif
+
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index a0b9e7c1e4fc..712fb5a6a568 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -16,13 +16,12 @@
#include <linux/irqflags.h>
#include <linux/types.h>
+#include <asm/asm.h>
#include <asm/barrier.h>
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/cmpxchg.h>
-#include <asm/llsc.h>
#include <asm/sync.h>
-#include <asm/war.h>
#define ATOMIC_OPS(pfx, type) \
static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
@@ -74,7 +73,7 @@ static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
"1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" " #sc " %0, %1 \n" \
- "\t" __SC_BEQZ "%0, 1b \n" \
+ "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i) : __LLSC_CLOBBER); \
@@ -104,7 +103,7 @@ arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
"1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
" " #asm_op " %0, %1, %3 \n" \
" " #sc " %0, %2 \n" \
- "\t" __SC_BEQZ "%0, 1b \n" \
+ "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set pop \n" \
: "=&r" (result), "=&r" (temp), \
@@ -137,7 +136,7 @@ arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
"1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
" " #asm_op " %0, %1, %3 \n" \
" " #sc " %0, %2 \n" \
- "\t" __SC_BEQZ "%0, 1b \n" \
+ "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
" move %0, %1 \n" \
: "=&r" (result), "=&r" (temp), \
@@ -237,7 +236,7 @@ static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " #sc " %1, %2 \n" \
- " " __SC_BEQZ "%1, 1b \n" \
+ " " __stringify(SC_BEQZ) " %1, 1b \n" \
"2: " __SYNC(full, loongson3_war) " \n" \
" .set pop \n" \
: "=&r" (result), "=&r" (temp), \
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index dc2a6234dd3c..3812082b8295 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -16,14 +16,12 @@
#include <linux/bits.h>
#include <linux/compiler.h>
#include <linux/types.h>
+#include <asm/asm.h>
#include <asm/barrier.h>
#include <asm/byteorder.h> /* sigh ... */
#include <asm/compiler.h>
#include <asm/cpu-features.h>
-#include <asm/isa-rev.h>
-#include <asm/llsc.h>
#include <asm/sgidefs.h>
-#include <asm/war.h>
#define __bit_op(mem, insn, inputs...) do { \
unsigned long __temp; \
@@ -32,10 +30,10 @@
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
- "1: " __LL "%0, %1 \n" \
+ "1: " __stringify(LONG_LL) " %0, %1 \n" \
" " insn " \n" \
- " " __SC "%0, %1 \n" \
- " " __SC_BEQZ "%0, 1b \n" \
+ " " __stringify(LONG_SC) " %0, %1 \n" \
+ " " __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
: "=&r"(__temp), "+" GCC_OFF_SMALL_ASM()(mem) \
: inputs \
@@ -49,10 +47,10 @@
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
- "1: " __LL ll_dst ", %2 \n" \
+ "1: " __stringify(LONG_LL) " " ll_dst ", %2\n" \
" " insn " \n" \
- " " __SC "%1, %2 \n" \
- " " __SC_BEQZ "%1, 1b \n" \
+ " " __stringify(LONG_SC) " %1, %2 \n" \
+ " " __stringify(SC_BEQZ) " %1, 1b \n" \
" .set pop \n" \
: "=&r"(__orig), "=&r"(__temp), \
"+" GCC_OFF_SMALL_ASM()(mem) \
@@ -98,7 +96,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
}
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) {
- __bit_op(*m, __INS "%0, %3, %2, 1", "i"(bit), "r"(~0));
+ __bit_op(*m, __stringify(LONG_INS) " %0, %3, %2, 1", "i"(bit), "r"(~0));
return;
}
@@ -126,7 +124,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
}
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) {
- __bit_op(*m, __INS "%0, $0, %2, 1", "i"(bit));
+ __bit_op(*m, __stringify(LONG_INS) " %0, $0, %2, 1", "i"(bit));
return;
}
@@ -234,8 +232,8 @@ static inline int test_and_clear_bit(unsigned long nr,
res = __mips_test_and_clear_bit(nr, addr);
} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
res = __test_bit_op(*m, "%1",
- __EXT "%0, %1, %3, 1;"
- __INS "%1, $0, %3, 1",
+ __stringify(LONG_EXT) " %0, %1, %3, 1;"
+ __stringify(LONG_INS) " %1, $0, %3, 1",
"i"(bit));
} else {
orig = __test_bit_op(*m, "%0",
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 66a8b293fd80..7ec9493b2861 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -10,10 +10,9 @@
#include <linux/bug.h>
#include <linux/irqflags.h>
+#include <asm/asm.h>
#include <asm/compiler.h>
-#include <asm/llsc.h>
#include <asm/sync.h>
-#include <asm/war.h>
/*
* These functions doesn't exist, so if they are called you'll either:
@@ -48,7 +47,7 @@ extern unsigned long __xchg_called_with_bad_pointer(void)
" move $1, %z3 \n" \
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
" " st " $1, %1 \n" \
- "\t" __SC_BEQZ "$1, 1b \n" \
+ "\t" __stringify(SC_BEQZ) " $1, 1b \n" \
" .set pop \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
@@ -127,7 +126,7 @@ unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
" move $1, %z4 \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
" " st " $1, %1 \n" \
- "\t" __SC_BEQZ "$1, 1b \n" \
+ "\t" __stringify(SC_BEQZ) " $1, 1b \n" \
" .set pop \n" \
"2: " __SYNC(full, loongson3_war) " \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
@@ -282,7 +281,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
/* Attempt to store new at ptr */
" scd %L1, %2 \n"
/* If we failed, loop! */
- "\t" __SC_BEQZ "%L1, 1b \n"
+ "\t" __stringify(SC_BEQZ) " %L1, 1b \n"
"2: " __SYNC(full, loongson3_war) " \n"
" .set pop \n"
: "=&r"(ret),
diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h
index 4f2302267deb..b4e210d633c2 100644
--- a/arch/mips/include/asm/kgdb.h
+++ b/arch/mips/include/asm/kgdb.h
@@ -18,7 +18,7 @@
#ifdef CONFIG_32BIT
#define KGDB_GDB_REG_SIZE 32
#define GDB_SIZEOF_REG sizeof(u32)
-#else /* CONFIG_CPU_32BIT */
+#else /* CONFIG_32BIT */
#define KGDB_GDB_REG_SIZE 64
#define GDB_SIZEOF_REG sizeof(u64)
#endif
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 696f6b009377..999bdd4f25b4 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -20,6 +20,7 @@
#include <linux/threads.h>
#include <linux/spinlock.h>
+#include <asm/asm.h>
#include <asm/inst.h>
#include <asm/mipsregs.h>
@@ -379,9 +380,9 @@ static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- " " __LL "%0, %1 \n"
+ " "__stringify(LONG_LL) " %0, %1 \n"
" or %0, %2 \n"
- " " __SC "%0, %1 \n"
+ " "__stringify(LONG_SC) " %0, %1 \n"
" .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (val));
@@ -396,9 +397,9 @@ static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- " " __LL "%0, %1 \n"
+ " "__stringify(LONG_LL) " %0, %1 \n"
" and %0, %2 \n"
- " " __SC "%0, %1 \n"
+ " "__stringify(LONG_SC) " %0, %1 \n"
" .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (~val));
@@ -414,10 +415,10 @@ static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- " " __LL "%0, %1 \n"
+ " "__stringify(LONG_LL) " %0, %1 \n"
" and %0, %2 \n"
" or %0, %3 \n"
- " " __SC "%0, %1 \n"
+ " "__stringify(LONG_SC) " %0, %1 \n"
" .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (~change), "r" (val & change));
diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h
deleted file mode 100644
index ec09fe5d6d6c..000000000000
--- a/arch/mips/include/asm/llsc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Macros for 32/64-bit neutral inline assembler
- */
-
-#ifndef __ASM_LLSC_H
-#define __ASM_LLSC_H
-
-#include <asm/isa-rev.h>
-
-#if _MIPS_SZLONG == 32
-#define __LL "ll "
-#define __SC "sc "
-#define __INS "ins "
-#define __EXT "ext "
-#elif _MIPS_SZLONG == 64
-#define __LL "lld "
-#define __SC "scd "
-#define __INS "dins "
-#define __EXT "dext "
-#endif
-
-/*
- * Using a branch-likely instruction to check the result of an sc instruction
- * works around a bug present in R10000 CPUs prior to revision 3.0 that could
- * cause ll-sc sequences to execute non-atomically.
- */
-#ifdef CONFIG_WAR_R10000_LLSC
-# define __SC_BEQZ "beqzl "
-#elif MIPS_ISA_REV >= 6
-# define __SC_BEQZ "beqzc "
-#else
-# define __SC_BEQZ "beqz "
-#endif
-
-#endif /* __ASM_LLSC_H */
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index ecda7295ddcd..08366b1fd273 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -5,9 +5,9 @@
#include <linux/percpu.h>
#include <linux/bitops.h>
#include <linux/atomic.h>
+#include <asm/asm.h>
#include <asm/cmpxchg.h>
#include <asm/compiler.h>
-#include <asm/war.h>
typedef struct
{
@@ -31,34 +31,18 @@ static __inline__ long local_add_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set arch=r4000 \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_add_return \n"
- " addu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " .set pop \n"
- : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
- : "Ir" (i), "m" (l->a.counter)
- : "memory");
- } else if (kernel_uses_llsc) {
+ if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_add_return \n"
- " addu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqz %0, 1b \n"
- " addu %0, %1, %3 \n"
+ __SYNC(full, loongson3_war) " \n"
+ "1:" __stringify(LONG_LL) " %1, %2 \n"
+ __stringify(LONG_ADDU) " %0, %1, %3 \n"
+ __stringify(LONG_SC) " %0, %2 \n"
+ __stringify(SC_BEQZ) " %0, 1b \n"
+ __stringify(LONG_ADDU) " %0, %1, %3 \n"
" .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
@@ -80,34 +64,19 @@ static __inline__ long local_sub_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set arch=r4000 \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_sub_return \n"
- " subu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " .set pop \n"
- : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
- : "Ir" (i), "m" (l->a.counter)
- : "memory");
- } else if (kernel_uses_llsc) {
+ if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_sub_return \n"
- " subu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqz %0, 1b \n"
- " subu %0, %1, %3 \n"
+ __SYNC(full, loongson3_war) " \n"
+ "1:" __stringify(LONG_LL) " %1, %2 \n"
+ __stringify(LONG_SUBU) " %0, %1, %3 \n"
+ __stringify(LONG_SUBU) " %0, %1, %3 \n"
+ __stringify(LONG_SC) " %0, %2 \n"
+ __stringify(SC_BEQZ) " %0, 1b \n"
+ __stringify(LONG_SUBU) " %0, %1, %3 \n"
" .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index f879be3e8099..6583639fe760 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -72,6 +72,7 @@ enum bcm47xx_board {
BCM47XX_BOARD_LINKSYS_WRT300NV11,
BCM47XX_BOARD_LINKSYS_WRT310NV1,
BCM47XX_BOARD_LINKSYS_WRT310NV2,
+ BCM47XX_BOARD_LINKSYS_WRT320N_V1,
BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
@@ -99,9 +100,12 @@ enum bcm47xx_board {
BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
BCM47XX_BOARD_NETGEAR_R6200_V1,
+ BCM47XX_BOARD_NETGEAR_R6300_V1,
BCM47XX_BOARD_NETGEAR_WGR614V8,
BCM47XX_BOARD_NETGEAR_WGR614V9,
BCM47XX_BOARD_NETGEAR_WGR614_V10,
+ BCM47XX_BOARD_NETGEAR_WN2500RP_V1,
+ BCM47XX_BOARD_NETGEAR_WN2500RP_V2,
BCM47XX_BOARD_NETGEAR_WNDR3300,
BCM47XX_BOARD_NETGEAR_WNDR3400V1,
BCM47XX_BOARD_NETGEAR_WNDR3400V2,
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 13373c5144f8..efb41b351974 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -32,7 +32,7 @@
nop
/* Loongson-3A R2/R3 */
andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
+ slti t0, t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
bnez t0, 2f
nop
1:
@@ -63,7 +63,7 @@
nop
/* Loongson-3A R2/R3 */
andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
+ slti t0, t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
bnez t0, 2f
nop
1:
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index 98c7abf4484a..50b1b8f1e186 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -9,16 +9,8 @@
#define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x)
-#if defined(CONFIG_TOSHIBA_RBTX4939) && \
- IS_ENABLED(CONFIG_SMC91X) && \
- defined(__BIG_ENDIAN)
-#define NEEDS_TXX9_IOSWABW
-extern u16 (*ioswabw)(volatile u16 *a, u16 x);
-extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
-#else
#define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
#define __mem_ioswabw(a, x) (x)
-#endif
#define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
#define __mem_ioswabl(a, x) (x)
#define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
index fd43d876892e..c077e8d100f5 100644
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -7,6 +7,7 @@
#ifndef __MIPS_ASM_MIPS_CPS_H__
#define __MIPS_ASM_MIPS_CPS_H__
+#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/types.h>
@@ -112,14 +113,10 @@ static inline void clear_##unit##_##name(uint##sz##_t val) \
*/
static inline unsigned int mips_cps_numclusters(void)
{
- unsigned int num_clusters;
-
if (mips_cm_revision() < CM_REV_CM3_5)
return 1;
- num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
- num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
- return num_clusters;
+ return FIELD_GET(CM_GCR_CONFIG_NUM_CLUSTERS, read_gcr_config());
}
/**
@@ -169,7 +166,8 @@ static inline unsigned int mips_cps_numcores(unsigned int cluster)
return 0;
/* Add one before masking to handle 0xff indicating no cores */
- return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+ return FIELD_GET(CM_GCR_CONFIG_PCORES,
+ mips_cps_cluster_config(cluster) + 1);
}
/**
@@ -181,14 +179,11 @@ static inline unsigned int mips_cps_numcores(unsigned int cluster)
*/
static inline unsigned int mips_cps_numiocu(unsigned int cluster)
{
- unsigned int num_iocu;
-
if (!mips_cm_present())
return 0;
- num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
- num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
- return num_iocu;
+ return FIELD_GET(CM_GCR_CONFIG_NUMIOCU,
+ mips_cps_cluster_config(cluster));
}
/**
@@ -230,7 +225,7 @@ static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int co
mips_cm_unlock_other();
- return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
+ return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1);
}
#endif /* __MIPS_ASM_MIPS_CPS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 0e6bf220db61..6c61e0a63924 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -318,7 +318,7 @@ enum cvmx_chip_types_enum {
/* Functions to return string based on type */
#define ENUM_BRD_TYPE_CASE(x) \
- case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
+ case x: return (&#x[16]); /* Skip CVMX_BOARD_TYPE_ */
static inline const char *cvmx_board_type_to_string(enum
cvmx_board_types_enum type)
{
@@ -410,7 +410,7 @@ static inline const char *cvmx_board_type_to_string(enum
}
#define ENUM_CHIP_TYPE_CASE(x) \
- case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
+ case x: return (&#x[15]); /* Skip CVMX_CHIP_TYPE */
static inline const char *cvmx_chip_type_to_string(enum
cvmx_chip_types_enum type)
{
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
index c02fe823effc..61411619dff3 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mc.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -484,7 +484,7 @@
/*
- * Bank Address Address Bits Register (Table 6-22)
+ * Bank Address Bits Register (Table 6-22)
*/
#define S_MC_BA_RESERVED 0
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 65618ff1280c..864aea803984 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -101,6 +101,9 @@ static inline int register_vsmp_smp_ops(void)
#ifdef CONFIG_MIPS_MT_SMP
extern const struct plat_smp_ops vsmp_smp_ops;
+ if (!cpu_has_mipsmt)
+ return -ENODEV;
+
register_smp_ops(&vsmp_smp_ops);
return 0;
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h
index d45237befd3e..70284e90dc53 100644
--- a/arch/mips/include/asm/txx9/boards.h
+++ b/arch/mips/include/asm/txx9/boards.h
@@ -6,9 +6,3 @@ BOARD_VEC(jmr3927_vec)
BOARD_VEC(rbtx4927_vec)
BOARD_VEC(rbtx4937_vec)
#endif
-#ifdef CONFIG_TOSHIBA_RBTX4938
-BOARD_VEC(rbtx4938_vec)
-#endif
-#ifdef CONFIG_TOSHIBA_RBTX4939
-BOARD_VEC(rbtx4939_vec)
-#endif
diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
deleted file mode 100644
index 9c969dd3c6eb..000000000000
--- a/arch/mips/include/asm/txx9/rbtx4938.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Definitions for TX4937/TX4938
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_RBTX4938_H
-#define __ASM_TXX9_RBTX4938_H
-
-#include <asm/addrspace.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4938.h>
-
-/* Address map */
-#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
-#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
-#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
-#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
-#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
-#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
-#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
-#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
-#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
-#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
-#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
-#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
-#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
-#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
-#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
-#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
-#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
-#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
-#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
-#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
-#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
-#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
-#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
-#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
-
-/* Ethernet port address (Jumperless Mode (W12:Open)) */
-#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
-
-/* bits for ISTAT/IMASK/IMSTAT */
-#define RBTX4938_INTB_PCID 0
-#define RBTX4938_INTB_PCIC 1
-#define RBTX4938_INTB_PCIB 2
-#define RBTX4938_INTB_PCIA 3
-#define RBTX4938_INTB_RTC 4
-#define RBTX4938_INTB_ATA 5
-#define RBTX4938_INTB_MODEM 6
-#define RBTX4938_INTB_SWINT 7
-#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
-#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
-#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
-#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
-#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
-#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
-#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
-#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
-
-#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
-#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
-#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
-#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
-#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
-#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
-#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
-#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
-#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
-#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
-#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
-#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
-#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
-#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
-#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
-#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
-#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
-#define rbtx4938_softresetlock_addr \
- ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
-#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
-
-/*
- * IRQ mappings
- */
-
-#define RBTX4938_SOFT_INT0 0 /* not used */
-#define RBTX4938_SOFT_INT1 1 /* not used */
-#define RBTX4938_IRC_INT 2
-#define RBTX4938_TIMER_INT 7
-
-/* These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
- * IRQ hardware is supported.
- */
-#define RBTX4938_NR_IRQ_IOC 8
-
-#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
-#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
-#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
-
-#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
-#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
-#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
-#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
-#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
-#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
-#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
-#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
-#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
-#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
-#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
-#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
-#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
-#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
-#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
-#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
-#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
-#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
-#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
-#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
-#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
-#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
-#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
-#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
-
-
-/* IOC (PCI, etc) */
-#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
-/* Onboard 10M Ether */
-#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
-
-#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
-#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
-
-void rbtx4938_prom_init(void);
-void rbtx4938_irq_setup(void);
-struct pci_dev;
-int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
deleted file mode 100644
index 6157bfd90848..000000000000
--- a/arch/mips/include/asm/txx9/rbtx4939.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Definitions for RBTX4939
- *
- * (C) Copyright TOSHIBA CORPORATION 2005-2006
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_TXX9_RBTX4939_H
-#define __ASM_TXX9_RBTX4939_H
-
-#include <asm/addrspace.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/tx4939.h>
-
-/* Address map */
-#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
-#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
-#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
-#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
-#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
-#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
-#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
-#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
-#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
-#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
-#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000)
-#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002)
-#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004)
-#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006)
-#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000)
-#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000)
-#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002)
-#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004)
-#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006)
-#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008)
-#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a)
-#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000)
-#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002)
-#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004)
-#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006)
-#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008)
-#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a)
-#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
-#define RBTX4939_7SEG_ADDR(s, ch) \
- (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
-#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
-#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
-#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
-#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
-
-/* Ethernet port address */
-#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300)
-
-/* bits for IEN/IPOL/IFAC */
-#define RBTX4938_INTB_ISA0 0
-#define RBTX4938_INTB_ISA11 1
-#define RBTX4938_INTB_ISA12 2
-#define RBTX4938_INTB_ISA15 3
-#define RBTX4938_INTB_I2S 4
-#define RBTX4938_INTB_SW 5
-#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0)
-#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11)
-#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12)
-#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15)
-#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S)
-#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW)
-
-/* bits for PE1,PE2,PE3 */
-#define RBTX4939_PE1_ATA(ch) (0x01 << (ch))
-#define RBTX4939_PE1_RMII(ch) (0x04 << (ch))
-#define RBTX4939_PE2_SIO0 0x01
-#define RBTX4939_PE2_SIO2 0x02
-#define RBTX4939_PE2_SIO3 0x04
-#define RBTX4939_PE2_CIR 0x08
-#define RBTX4939_PE2_SPI 0x10
-#define RBTX4939_PE2_GPIO 0x20
-#define RBTX4939_PE3_VP 0x01
-#define RBTX4939_PE3_VP_P 0x02
-#define RBTX4939_PE3_VP_S 0x04
-
-#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
-#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
-#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
-#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
-#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
-#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
-#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR)
-#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
-#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
-#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR)
-#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR)
-#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
-#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
-#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
-#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
-#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
-#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR)
-#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR)
-#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR)
-#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
-#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR)
-#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR)
-#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR)
-#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR)
-#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
-#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
-#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
-#define rbtx4939_7seg_addr(s, ch) \
- ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
-#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
-#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
-#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
-
-/*
- * IRQ mappings
- */
-#define RBTX4939_NR_IRQ_IOC 8
-
-#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR)
-#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
-
-/* IOC (ISA, etc) */
-#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0))
-/* Onboard 10M Ether */
-#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1))
-
-void rbtx4939_prom_init(void);
-void rbtx4939_irq_setup(void);
-
-struct mtd_partition;
-struct map_info;
-struct rbtx4939_flash_data {
- unsigned int width;
- unsigned int nr_parts;
- struct mtd_partition *parts;
- void (*map_init)(struct map_info *map);
-};
-
-#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/arch/mips/include/asm/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h
deleted file mode 100644
index 0d727f354557..000000000000
--- a/arch/mips/include/asm/txx9/spi.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Definitions for TX4937/TX4938 SPI
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_SPI_H
-#define __ASM_TXX9_SPI_H
-
-#include <linux/errno.h>
-
-#ifdef CONFIG_SPI
-int spi_eeprom_register(int busid, int chipid, int size);
-int spi_eeprom_read(int busid, int chipid,
- int address, unsigned char *buf, int len);
-#else
-static inline int spi_eeprom_register(int busid, int chipid, int size)
-{
- return -ENODEV;
-}
-static inline int spi_eeprom_read(int busid, int chipid,
- int address, unsigned char *buf, int len)
-{
- return -ENODEV;
-}
-#endif
-
-#endif /* __ASM_TXX9_SPI_H */
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
deleted file mode 100644
index abf980af9ef4..000000000000
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * Definitions for TX4939
- *
- * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_TXX9_TX4939_H
-#define __ASM_TXX9_TX4939_H
-
-/* some controllers are compatible with 4927/4938 */
-#include <asm/txx9/tx4938.h>
-
-#ifdef CONFIG_64BIT
-#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
-#else
-#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
-#endif
-#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
-
-#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
-#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
-#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000)
-#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800)
-#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000)
-#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000)
-#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000)
-#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000)
-#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
-#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000)
-#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000)
-#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800)
-#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
-#define TX4939_TMR_REG(ch) \
- (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
-#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */
-#define TX4939_SIO_REG(ch) \
- (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
-#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700)
-#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800)
-#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900)
-#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00)
-#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
-#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
-
-#define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0)
-
-struct tx4939_le_reg {
- __u32 r;
- __u32 unused;
-};
-
-struct tx4939_ddrc_reg {
- struct tx4939_le_reg ctl[47];
- __u64 unused0[17];
- __u64 winen;
- __u64 win[4];
-};
-
-struct tx4939_ccfg_reg {
- __u64 ccfg;
- __u64 crir;
- __u64 pcfg;
- __u64 toea;
- __u64 clkctr;
- __u64 unused0;
- __u64 garbc;
- __u64 unused1[2];
- __u64 ramp;
- __u64 unused2[2];
- __u64 dskwctrl;
- __u64 mclkosc;
- __u64 mclkctl;
- __u64 unused3[17];
- struct {
- __u64 mr;
- __u64 dr;
- } gpio[2];
-};
-
-struct tx4939_irc_reg {
- struct tx4939_le_reg den;
- struct tx4939_le_reg scipb;
- struct tx4939_le_reg dm[2];
- struct tx4939_le_reg lvl[16];
- struct tx4939_le_reg msk;
- struct tx4939_le_reg edc;
- struct tx4939_le_reg pnd0;
- struct tx4939_le_reg cs;
- struct tx4939_le_reg pnd1;
- struct tx4939_le_reg dm2[2];
- struct tx4939_le_reg dbr[2];
- struct tx4939_le_reg dben;
- struct tx4939_le_reg unused0[2];
- struct tx4939_le_reg flag[2];
- struct tx4939_le_reg pol;
- struct tx4939_le_reg cnt;
- struct tx4939_le_reg maskint;
- struct tx4939_le_reg maskext;
-};
-
-struct tx4939_crypto_reg {
- struct tx4939_le_reg csr;
- struct tx4939_le_reg idesptr;
- struct tx4939_le_reg cdesptr;
- struct tx4939_le_reg buserr;
- struct tx4939_le_reg cip_tout;
- struct tx4939_le_reg cir;
- union {
- struct {
- struct tx4939_le_reg data[8];
- struct tx4939_le_reg ctrl;
- } gen;
- struct {
- struct {
- struct tx4939_le_reg l;
- struct tx4939_le_reg u;
- } key[3], ini;
- struct tx4939_le_reg ctrl;
- } des;
- struct {
- struct tx4939_le_reg key[4];
- struct tx4939_le_reg ini[4];
- struct tx4939_le_reg ctrl;
- } aes;
- struct {
- struct {
- struct tx4939_le_reg l;
- struct tx4939_le_reg u;
- } cnt;
- struct tx4939_le_reg ini[5];
- struct tx4939_le_reg unused;
- struct tx4939_le_reg ctrl;
- } hash;
- } cdr;
- struct tx4939_le_reg unused0[7];
- struct tx4939_le_reg rcsr;
- struct tx4939_le_reg rpr;
- __u64 rdr;
- __u64 ror[3];
- struct tx4939_le_reg unused1[2];
- struct tx4939_le_reg xorslr;
- struct tx4939_le_reg xorsur;
-};
-
-struct tx4939_crypto_desc {
- __u32 src;
- __u32 dst;
- __u32 next;
- __u32 ctrl;
- __u32 index;
- __u32 xor;
-};
-
-struct tx4939_vpc_reg {
- struct tx4939_le_reg csr;
- struct {
- struct tx4939_le_reg ctrlA;
- struct tx4939_le_reg ctrlB;
- struct tx4939_le_reg idesptr;
- struct tx4939_le_reg cdesptr;
- } port[3];
- struct tx4939_le_reg buserr;
-};
-
-struct tx4939_vpc_desc {
- __u32 src;
- __u32 next;
- __u32 ctrl1;
- __u32 ctrl2;
-};
-
-/*
- * IRC
- */
-#define TX4939_IR_NONE 0
-#define TX4939_IR_DDR 1
-#define TX4939_IR_WTOERR 2
-#define TX4939_NUM_IR_INT 3
-#define TX4939_IR_INT(n) (3 + (n))
-#define TX4939_NUM_IR_ETH 2
-#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
-#define TX4939_IR_VIDEO 7
-#define TX4939_IR_CIR 8
-#define TX4939_NUM_IR_SIO 4
-#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
-#define TX4939_NUM_IR_DMA 4
-#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
-#define TX4939_IR_IRC 14
-#define TX4939_IR_PDMAC 15
-#define TX4939_NUM_IR_TMR 6
-#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
-#define TX4939_NUM_IR_ATA 2
-#define TX4939_IR_ATA(n) (19 + (n))
-#define TX4939_IR_ACLC 21
-#define TX4939_IR_CIPHER 26
-#define TX4939_IR_INTA 27
-#define TX4939_IR_INTB 28
-#define TX4939_IR_INTC 29
-#define TX4939_IR_INTD 30
-#define TX4939_IR_I2C 33
-#define TX4939_IR_SPI 34
-#define TX4939_IR_PCIC 35
-#define TX4939_IR_PCIC1 36
-#define TX4939_IR_PCIERR 37
-#define TX4939_IR_PCIPME 38
-#define TX4939_IR_NDFMC 39
-#define TX4939_IR_ACLCPME 40
-#define TX4939_IR_RTC 41
-#define TX4939_IR_RND 42
-#define TX4939_IR_I2S 47
-#define TX4939_NUM_IR 64
-
-#define TX4939_IRC_INT 2 /* IP[2] in Status register */
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL
-#define TX4939_CCFG_WDRST 0x0000020000000000ULL
-#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL
-#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL
-#define TX4939_CCFG_GTOT_MASK 0x06000000
-#define TX4939_CCFG_GTOT_4096 0x06000000
-#define TX4939_CCFG_GTOT_2048 0x04000000
-#define TX4939_CCFG_GTOT_1024 0x02000000
-#define TX4939_CCFG_GTOT_512 0x00000000
-#define TX4939_CCFG_TINTDIS 0x01000000
-#define TX4939_CCFG_PCI66 0x00800000
-#define TX4939_CCFG_PCIMODE 0x00400000
-#define TX4939_CCFG_SSCG 0x00100000
-#define TX4939_CCFG_MULCLK_MASK 0x000e0000
-#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
-#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
-#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
-#define TX4939_CCFG_MULCLK_11 (0x2 << 17)
-#define TX4939_CCFG_MULCLK_12 (0x3 << 17)
-#define TX4939_CCFG_MULCLK_13 (0x4 << 17)
-#define TX4939_CCFG_MULCLK_14 (0x5 << 17)
-#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
-#define TX4939_CCFG_BEOW 0x00010000
-#define TX4939_CCFG_WR 0x00008000
-#define TX4939_CCFG_TOE 0x00004000
-#define TX4939_CCFG_PCIARB 0x00002000
-#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
-#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
-#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10)
-#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10)
-#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10)
-#define TX4939_CCFG_PTSEL 0x00000200
-#define TX4939_CCFG_BESEL 0x00000100
-#define TX4939_CCFG_SYSSP_MASK 0x000000c0
-#define TX4939_CCFG_ACKSEL 0x00000020
-#define TX4939_CCFG_ROMW 0x00000010
-#define TX4939_CCFG_ENDIAN 0x00000004
-#define TX4939_CCFG_ARMODE 0x00000002
-#define TX4939_CCFG_ACEHOLD 0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL
-#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL
-#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL
-#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL
-#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL
-#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
-#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
-#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
-#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
-#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
-#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
-#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
-#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL
-#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL
-#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL
-#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL
-#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL
-#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL
-#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL
-#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL
-#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL
-#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL
-
-#define TX4939_PCFG_SYSCLKEN 0x08000000
-#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000
-#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
-#define TX4939_PCFG_SPEED1 0x00002000
-#define TX4939_PCFG_SPEED0 0x00001000
-#define TX4939_PCFG_ITMODE 0x00000300
-#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3)
-#define TX4939_PCFG_DMASEL2 0x00000004
-#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000
-#define TX4939_PCFG_DMASEL2_SIO0 0x00000004
-#define TX4939_PCFG_DMASEL1 0x00000002
-#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000
-#define TX4939_PCFG_DMASEL0 0x00000001
-#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000
-
-/* CLKCTR : Clock Control */
-#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL
-#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL
-#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL
-#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL
-#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL
-#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL
-#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL
-#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL
-#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL
-#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL
-#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL
-#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL
-#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL
-#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL
-#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL
-#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL
-#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL
-#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL
-#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL
-#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL
-#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL
-#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL
-#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL
-#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL
-#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL
-#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL
-#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL
-#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL
-#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL
-#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL
-#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL
-#define TX4939_CLKCTR_IOSRST 0x80000000
-#define TX4939_CLKCTR_SYSRST 0x40000000
-#define TX4939_CLKCTR_TM5RST 0x20000000
-#define TX4939_CLKCTR_TM4RST 0x10000000
-#define TX4939_CLKCTR_TM3RST 0x08000000
-#define TX4939_CLKCTR_CIRRST 0x04000000
-#define TX4939_CLKCTR_SIO3RST 0x02000000
-#define TX4939_CLKCTR_SIO2RST 0x01000000
-#define TX4939_CLKCTR_SIO1RST 0x00800000
-#define TX4939_CLKCTR_VPCRST 0x00400000
-#define TX4939_CLKCTR_EPCIRST 0x00200000
-#define TX4939_CLKCTR_ETH1RST 0x00080000
-#define TX4939_CLKCTR_ATA1RST 0x00040000
-#define TX4939_CLKCTR_BROMRST 0x00020000
-#define TX4939_CLKCTR_NDCRST 0x00010000
-#define TX4939_CLKCTR_I2CRST 0x00008000
-#define TX4939_CLKCTR_ETH0RST 0x00004000
-#define TX4939_CLKCTR_SPIRST 0x00002000
-#define TX4939_CLKCTR_SRAMRST 0x00001000
-#define TX4939_CLKCTR_PCI1RST 0x00000800
-#define TX4939_CLKCTR_DMA1RST 0x00000400
-#define TX4939_CLKCTR_ACLRST 0x00000200
-#define TX4939_CLKCTR_ATA0RST 0x00000100
-#define TX4939_CLKCTR_DMA0RST 0x00000080
-#define TX4939_CLKCTR_PCICRST 0x00000040
-#define TX4939_CLKCTR_I2SRST 0x00000020
-#define TX4939_CLKCTR_TM0RST 0x00000010
-#define TX4939_CLKCTR_TM1RST 0x00000008
-#define TX4939_CLKCTR_TM2RST 0x00000004
-#define TX4939_CLKCTR_SIO0RST 0x00000002
-#define TX4939_CLKCTR_CYPRST 0x00000001
-
-/*
- * CRYPTO
- */
-#define TX4939_CRYPTO_CSR_SAESO 0x08000000
-#define TX4939_CRYPTO_CSR_SAESI 0x04000000
-#define TX4939_CRYPTO_CSR_SDESO 0x02000000
-#define TX4939_CRYPTO_CSR_SDESI 0x01000000
-#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
-#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
-#define TX4939_CRYPTO_CSR_TOINT 0x00080000
-#define TX4939_CRYPTO_CSR_DCINT 0x00040000
-#define TX4939_CRYPTO_CSR_GBINT 0x00010000
-#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
-#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
-#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
-#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000
-#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800
-#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000
-#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800
-#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600
-#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000
-#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200
-#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400
-#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600
-#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0
-#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000
-#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
-#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
-#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
-#define TX4939_CRYPTO_CSR_GINTE 0x00000008
-#define TX4939_CRYPTO_CSR_RSTD 0x00000004
-#define TX4939_CRYPTO_CSR_RSTC 0x00000002
-#define TX4939_CRYPTO_CSR_ENCR 0x00000001
-
-/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
-#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003
-#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000
-#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001
-#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002
-#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003
-#define TX4939_CRYPTO_CTX_TDMS 0x00000010
-#define TX4939_CRYPTO_CTX_CMS 0x00000020
-#define TX4939_CRYPTO_CTX_DMS 0x00000040
-#define TX4939_CRYPTO_CTX_UPDATE 0x00000080
-
-/* bits for tx4939_crypto_desc.ctrl */
-#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000
-#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21)
-#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00
-#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10)
-#define TX4939_CRYPTO_DESC_START 0x00000200
-#define TX4939_CRYPTO_DESC_END 0x00000100
-#define TX4939_CRYPTO_DESC_XOR 0x00000010
-#define TX4939_CRYPTO_DESC_LAST 0x00000008
-#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
-#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
-#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
-#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004
-#define TX4939_CRYPTO_DESC_OWN 0x00000001
-
-/* bits for tx4939_crypto_desc.index */
-#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070
-#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4)
-#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007
-#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0)
-
-#define TX4939_CRYPTO_NR_SET 6
-
-#define TX4939_CRYPTO_RCSR_INTE 0x00000008
-#define TX4939_CRYPTO_RCSR_RST 0x00000004
-#define TX4939_CRYPTO_RCSR_FIN 0x00000002
-#define TX4939_CRYPTO_RCSR_ST 0x00000001
-
-/*
- * VPC
- */
-#define TX4939_VPC_CSR_GBINT 0x00010000
-#define TX4939_VPC_CSR_SWAPO 0x00000020
-#define TX4939_VPC_CSR_SWAPI 0x00000010
-#define TX4939_VPC_CSR_GINTE 0x00000008
-#define TX4939_VPC_CSR_RSTD 0x00000004
-#define TX4939_VPC_CSR_RSTVPC 0x00000002
-
-#define TX4939_VPC_CTRLA_VDPSN 0x00000200
-#define TX4939_VPC_CTRLA_PBUSY 0x00000100
-#define TX4939_VPC_CTRLA_DCINT 0x00000080
-#define TX4939_VPC_CTRLA_UOINT 0x00000040
-#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030
-#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
-#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
-#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
-#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
-#define TX4939_VPC_CTRLA_VDMODE 0x00000004
-#define TX4939_VPC_CTRLA_VDFOR 0x00000002
-#define TX4939_VPC_CTRLA_ENVPC 0x00000001
-
-/* bits for tx4939_vpc_desc.ctrl1 */
-#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006
-#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001
-
-#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
-#define tx4939_ebuscptr tx4938_ebuscptr
-#define tx4939_ircptr \
- ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
-#define tx4939_pcicptr tx4938_pcicptr
-#define tx4939_pcic1ptr tx4938_pcic1ptr
-#define tx4939_ccfgptr \
- ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
-#define tx4939_sramcptr tx4938_sramcptr
-#define tx4939_cryptoptr \
- ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
-#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
-
-#define TX4939_REV_MAJ_MIN() \
- ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
-#define TX4939_REV_PCODE() \
- ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
-#define TX4939_CCFG_BCFG() \
- ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
- >> 32))
-
-#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
-#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
-#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
-
-#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
-#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
-#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
-#define TX4939_EBUSC_WIDTH(ch) \
- (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
-
-/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
-#define TX4939_SCLK0(mst) \
- ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
-
-void tx4939_wdt_init(void);
-void tx4939_setup(void);
-void tx4939_time_init(unsigned int tmrnr);
-void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
-void tx4939_spi_init(int busid);
-void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
-int tx4939_report_pciclk(void);
-void tx4939_report_pci1clk(void);
-struct pci_dev;
-int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
-int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-void tx4939_setup_pcierr_irq(void);
-void tx4939_irq_init(void);
-int tx4939_irq(void);
-void tx4939_mtd_init(int ch);
-void tx4939_ata_init(void);
-void tx4939_rtc_init(void);
-void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
- unsigned char ch_mask, unsigned char wide_mask);
-void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
-void tx4939_aclc_init(void);
-void tx4939_sramc_init(void);
-void tx4939_rng_init(void);
-
-#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 8d2535123f11..17aff13cd7ce 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -4,6 +4,7 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
+#include <linux/bitfield.h>
#include <linux/errno.h>
#include <linux/percpu.h>
#include <linux/of.h>
@@ -97,7 +98,7 @@ void mips_cpc_lock_other(unsigned int core)
curr_core = cpu_core(¤t_cpu_data);
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
- write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
+ write_cpc_cl_other(FIELD_PREP(CPC_Cx_OTHER_CORENUM, core));
/*
* Ensure the core-other region reflects the appropriate core &
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index c9b2a75563e1..5bce782e694c 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -562,6 +562,13 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
/* Default to using normal stack */
sp = regs->regs[29];
+ /*
+ * If we are on the alternate signal stack and would overflow it, don't.
+ * Return an always-bogus address instead so we will die with SIGSEGV.
+ */
+ if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size)))
+ return (void __user __force *)(-1UL);
+
/*
* FPU emulator may have it's own trampoline active just
* above the user stack, 16-bytes before the next lowest
@@ -747,23 +754,25 @@ static int setup_rt_frame(void *sig_return, struct ksignal *ksig,
struct pt_regs *regs, sigset_t *set)
{
struct rt_sigframe __user *frame;
- int err = 0;
frame = get_sigframe(ksig, regs, sizeof(*frame));
if (!access_ok(frame, sizeof (*frame)))
return -EFAULT;
/* Create siginfo. */
- err |= copy_siginfo_to_user(&frame->rs_info, &ksig->info);
+ if (copy_siginfo_to_user(&frame->rs_info, &ksig->info))
+ return -EFAULT;
/* Create the ucontext. */
- err |= __put_user(0, &frame->rs_uc.uc_flags);
- err |= __put_user(NULL, &frame->rs_uc.uc_link);
- err |= __save_altstack(&frame->rs_uc.uc_stack, regs->regs[29]);
- err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
- err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
+ if (__put_user(0, &frame->rs_uc.uc_flags))
+ return -EFAULT;
+ if (__put_user(NULL, &frame->rs_uc.uc_link))
+ return -EFAULT;
+ if (__save_altstack(&frame->rs_uc.uc_stack, regs->regs[29]))
+ return -EFAULT;
+ if (setup_sigcontext(regs, &frame->rs_uc.uc_mcontext))
+ return -EFAULT;
+ if (__copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set)))
return -EFAULT;
/*
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 4916cccf378f..7a623684d9b5 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -164,6 +164,12 @@ struct clk *clk_get_parent(struct clk *clk)
}
EXPORT_SYMBOL(clk_get_parent);
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
static inline u32 get_counter_resolution(void)
{
u32 res;
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 42222f849bd2..64726c670ca6 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -141,7 +141,7 @@ static void falcon_gpe_enable(void)
unsigned int freq;
unsigned int status;
- /* if if the clock is already enabled */
+ /* if the clock is already enabled */
status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
if (status & (1 << (GPPC_OFFSET + 1)))
return;
diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform
index ae023b9a1c51..50e659aca543 100644
--- a/arch/mips/loongson2ef/Platform
+++ b/arch/mips/loongson2ef/Platform
@@ -2,12 +2,9 @@
# Loongson Processors' Support
#
-# Only gcc >= 4.4 have Loongson specific support
cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
- $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
- $(call cc-option,-march=loongson2f,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e
+cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
@@ -32,16 +29,8 @@ cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call as-option,-Wa$(comma)-mno-fix-loongso
# Enable the workarounds for Loongson2f
ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
- else
- cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
- endif
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
- else
- cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
- endif
+cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
+cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
endif
# Some -march= flags enable MMI instructions, and GCC complains about that
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index ec2ae501539a..737870d8fd94 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -332,7 +332,7 @@ static void co_cache_error_call_notifiers(unsigned long val)
}
/*
- * Called when the the exception is recoverable
+ * Called when the exception is recoverable
*/
asmlinkage void cache_parity_error_octeon_recoverable(void)
@@ -341,7 +341,7 @@ asmlinkage void cache_parity_error_octeon_recoverable(void)
}
/*
- * Called when the the exception is not recoverable
+ * Called when the exception is not recoverable
*/
asmlinkage void cache_parity_error_octeon_non_recoverable(void)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 6ddefafd00cb..9a6bc702608c 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -49,9 +49,7 @@ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
-obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
-obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c
deleted file mode 100644
index ff22a22db73e..000000000000
--- a/arch/mips/pci/fixup-rbtx4938.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Toshiba rbtx4938 pci routines
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#include <linux/types.h>
-#include <asm/txx9/pci.h>
-#include <asm/txx9/rbtx4938.h>
-
-int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = tx4938_pcic1_map_irq(dev, slot);
-
- if (irq >= 0)
- return irq;
- irq = pin;
- /* IRQ rotation */
- irq--; /* 0-3 */
- if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
- /* PCI CardSlot (IDSEL=A23) */
- /* PCIA => PCIA (IDSEL=A23) */
- irq = (irq + 0 + slot) % 4;
- } else {
- /* PCI Backplane */
- if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
- irq = (irq + 33 - slot) % 4;
- else
- irq = (irq + 3 + slot) % 4;
- }
- irq++; /* 1-4 */
-
- switch (irq) {
- case 1:
- irq = RBTX4938_IRQ_IOC_PCIA;
- break;
- case 2:
- irq = RBTX4938_IRQ_IOC_PCIB;
- break;
- case 3:
- irq = RBTX4938_IRQ_IOC_PCIC;
- break;
- case 4:
- irq = RBTX4938_IRQ_IOC_PCID;
- break;
- }
- return irq;
-}
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index d3c947fa2969..e07ae098bdd8 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -102,14 +102,12 @@ static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
unsigned func, unsigned reg)
{
u32 address;
- u32 ret;
address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
- ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
- return ret;
+ return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
}
static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
deleted file mode 100644
index 09a65f7dbe7c..000000000000
--- a/arch/mips/pci/pci-tx4939.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
- * and RBTX49xx patch from CELF patch archive.
- *
- * Copyright 2001, 2003-2005 MontaVista Software Inc.
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/tx4939.h>
-
-int __init tx4939_report_pciclk(void)
-{
- int pciclk = 0;
-
- pr_info("PCIC --%s PCICLK:",
- (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
- " PCI66" : "");
- if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
- pciclk = txx9_master_clock * 20 / 6;
- if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
- pciclk /= 2;
- pr_cont("Internal(%u.%uMHz)",
- (pciclk + 50000) / 1000000,
- ((pciclk + 50000) / 100000) % 10);
- } else {
- pr_cont("External");
- pciclk = -1;
- }
- pr_cont("\n");
- return pciclk;
-}
-
-void __init tx4939_report_pci1clk(void)
-{
- unsigned int pciclk = txx9_master_clock * 20 / 6;
-
- pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
- (pciclk + 50000) / 1000000,
- ((pciclk + 50000) / 100000) % 10);
-}
-
-int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
-{
- if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
- switch (slot) {
- case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
- if (__raw_readq(&tx4939_ccfgptr->pcfg) &
- TX4939_PCFG_ET0MODE)
- return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
- break;
- case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
- if (__raw_readq(&tx4939_ccfgptr->pcfg) &
- TX4939_PCFG_ET1MODE)
- return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
- break;
- }
- return 0;
- }
- return -1;
-}
-
-int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = tx4939_pcic1_map_irq(dev, slot);
-
- if (irq >= 0)
- return irq;
- irq = pin;
- /* IRQ rotation */
- irq--; /* 0-3 */
- irq = (irq + 33 - slot) % 4;
- irq++; /* 1-4 */
-
- switch (irq) {
- case 1:
- irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
- break;
- case 2:
- irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
- break;
- case 3:
- irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
- break;
- case 4:
- irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
- break;
- }
- return irq;
-}
-
-void __init tx4939_setup_pcierr_irq(void)
-{
- if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
- tx4927_pcierr_interrupt,
- 0, "PCI error",
- (void *)TX4939_PCIC_REG))
- pr_warn("Failed to request irq for PCIERR\n");
-}
diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
index bdf53807d7c2..115a69fc20ca 100644
--- a/arch/mips/ralink/ill_acc.c
+++ b/arch/mips/ralink/ill_acc.c
@@ -65,6 +65,7 @@ static int __init ill_acc_of_setup(void)
}
irq = irq_of_parse_and_map(np, 0);
+ of_node_put(np);
if (!irq) {
dev_err(&pdev->dev, "failed to get irq\n");
put_device(&pdev->dev);
diff --git a/arch/mips/sgi-ip22/Platform b/arch/mips/sgi-ip22/Platform
index 62fa30bb959e..a4c46e33562e 100644
--- a/arch/mips/sgi-ip22/Platform
+++ b/arch/mips/sgi-ip22/Platform
@@ -23,10 +23,5 @@ endif
# be 16kb aligned or the handling of the current variable will break.
# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
#
-ifdef CONFIG_SGI_IP28
- ifeq ($(call cc-option-yn,-march=r10000 -mr10k-cache-barrier=store), n)
- $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
- endif
-endif
cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
load-$(CONFIG_SGI_IP28) += 0xa800000020004000
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 85c4c121c71f..6c61feee6dd3 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -6,6 +6,7 @@ config MACH_TX39XX
config MACH_TX49XX
bool
+ select BOOT_ELF32
select MACH_TXX9
select CEVT_R4K
select CSRC_R4K
@@ -38,23 +39,6 @@ config TOSHIBA_RBTX4927
This Toshiba board is based on the TX4927 processor. Say Y here to
support this machine type
-config TOSHIBA_RBTX4938
- bool "Toshiba RBTX4938 board"
- depends on MACH_TX49XX
- select SOC_TX4938
- help
- This Toshiba board is based on the TX4938 processor. Say Y here to
- support this machine type
-
-config TOSHIBA_RBTX4939
- bool "Toshiba RBTX4939 board"
- depends on MACH_TX49XX
- select SOC_TX4939
- select TXX9_7SEGLED
- help
- This Toshiba board is based on the TX4939 processor. Say Y here to
- support this machine type
-
config SOC_TX3927
bool
select CEVT_TXX9
@@ -71,7 +55,6 @@ config SOC_TX4927
select IRQ_TXX9
select PCI_TX4927
select GPIO_TXX9
- imply HAS_TXX9_ACLC
config SOC_TX4938
bool
@@ -81,18 +64,6 @@ config SOC_TX4938
select IRQ_TXX9
select PCI_TX4927
select GPIO_TXX9
- imply HAS_TXX9_ACLC
-
-config SOC_TX4939
- bool
- select CEVT_TXX9
- imply HAS_TXX9_SERIAL
- select HAVE_PCI
- select PCI_TX4927
- imply HAS_TXX9_ACLC
-
-config TXX9_7SEGLED
- bool
config TOSHIBA_FPCIB0
bool "FPCIB0 Backplane Support"
@@ -104,25 +75,5 @@ config PICMG_PCI_BACKPLANE_DEFAULT
depends on PCI && MACH_TXX9
default y if !TOSHIBA_FPCIB0
-if TOSHIBA_RBTX4938
-
-comment "Multiplex Pin Select"
-choice
- prompt "PIO[58:61]"
- default TOSHIBA_RBTX4938_MPLEX_PIO58_61
-
-config TOSHIBA_RBTX4938_MPLEX_PIO58_61
- bool "PIO"
-config TOSHIBA_RBTX4938_MPLEX_NAND
- bool "NAND"
-config TOSHIBA_RBTX4938_MPLEX_ATA
- bool "ATA"
-config TOSHIBA_RBTX4938_MPLEX_KEEP
- bool "Keep firmware settings"
-
-endchoice
-
-endif
-
config PCI_TX4927
bool
diff --git a/arch/mips/txx9/Makefile b/arch/mips/txx9/Makefile
index 195295937282..53269910a48b 100644
--- a/arch/mips/txx9/Makefile
+++ b/arch/mips/txx9/Makefile
@@ -14,5 +14,3 @@ obj-$(CONFIG_TOSHIBA_JMR3927) += jmr3927/
# Toshiba RBTX49XX boards
#
obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
-obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
-obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c
deleted file mode 100644
index 2203c2548cb4..000000000000
--- a/arch/mips/txx9/generic/7segled.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * 7 Segment LED routines
- * Based on RBTX49xx patch from CELF patch archive.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright TOSHIBA CORPORATION 2005-2007
- * All Rights Reserved.
- */
-#include <linux/device.h>
-#include <linux/slab.h>
-#include <linux/map_to_7segment.h>
-#include <asm/txx9/generic.h>
-
-static unsigned int tx_7segled_num;
-static void (*tx_7segled_putc)(unsigned int pos, unsigned char val);
-
-void __init txx9_7segled_init(unsigned int num,
- void (*putc)(unsigned int pos, unsigned char val))
-{
- tx_7segled_num = num;
- tx_7segled_putc = putc;
-}
-
-static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC);
-
-int txx9_7segled_putc(unsigned int pos, char c)
-{
- if (pos >= tx_7segled_num)
- return -EINVAL;
- c = map_to_seg7(&txx9_seg7map, c);
- if (c < 0)
- return c;
- tx_7segled_putc(pos, c);
- return 0;
-}
-
-static ssize_t ascii_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t size)
-{
- unsigned int ch = dev->id;
- txx9_7segled_putc(ch, buf[0]);
- return size;
-}
-
-static ssize_t raw_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t size)
-{
- unsigned int ch = dev->id;
- tx_7segled_putc(ch, buf[0]);
- return size;
-}
-
-static DEVICE_ATTR_WO(ascii);
-static DEVICE_ATTR_WO(raw);
-
-static ssize_t map_seg7_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map));
- return sizeof(txx9_seg7map);
-}
-
-static ssize_t map_seg7_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t size)
-{
- if (size != sizeof(txx9_seg7map))
- return -EINVAL;
- memcpy(&txx9_seg7map, buf, size);
- return size;
-}
-
-static DEVICE_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store);
-
-static struct bus_type tx_7segled_subsys = {
- .name = "7segled",
- .dev_name = "7segled",
-};
-
-static void tx_7segled_release(struct device *dev)
-{
- kfree(dev);
-}
-
-static int __init tx_7segled_init_sysfs(void)
-{
- int error, i;
- if (!tx_7segled_num)
- return -ENODEV;
- error = subsys_system_register(&tx_7segled_subsys, NULL);
- if (error)
- return error;
- error = device_create_file(tx_7segled_subsys.dev_root, &dev_attr_map_seg7);
- if (error)
- return error;
- for (i = 0; i < tx_7segled_num; i++) {
- struct device *dev;
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
- if (!dev) {
- error = -ENODEV;
- break;
- }
- dev->id = i;
- dev->bus = &tx_7segled_subsys;
- dev->release = &tx_7segled_release;
- error = device_register(dev);
- if (error) {
- put_device(dev);
- return error;
- }
- device_create_file(dev, &dev_attr_ascii);
- device_create_file(dev, &dev_attr_raw);
- }
- return error;
-}
-
-device_initcall(tx_7segled_init_sysfs);
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 6d00580fc81d..be5af9fe7c11 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -8,7 +8,4 @@ obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
-obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
-obj-$(CONFIG_SPI) += spi_eeprom.o
-obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
deleted file mode 100644
index 0d7267e81a8c..000000000000
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * TX4939 irq routines
- * Based on linux/arch/mips/kernel/irq_txx9.c,
- * and RBTX49xx patch from CELF patch archive.
- *
- * Copyright 2001, 2003-2005 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ahennessy@mvista.com
- * source@mvista.com
- * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-/*
- * TX4939 defines 64 IRQs.
- * Similer to irq_txx9.c but different register layouts.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <asm/irq_cpu.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4939.h>
-
-/* IRCER : Int. Control Enable */
-#define TXx9_IRCER_ICE 0x00000001
-
-/* IRCR : Int. Control */
-#define TXx9_IRCR_LOW 0x00000000
-#define TXx9_IRCR_HIGH 0x00000001
-#define TXx9_IRCR_DOWN 0x00000002
-#define TXx9_IRCR_UP 0x00000003
-#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
-
-/* IRSCR : Int. Status Control */
-#define TXx9_IRSCR_EIClrE 0x00000100
-#define TXx9_IRSCR_EIClr_MASK 0x0000000f
-
-/* IRCSR : Int. Current Status */
-#define TXx9_IRCSR_IF 0x00010000
-
-#define irc_dlevel 0
-#define irc_elevel 1
-
-static struct {
- unsigned char level;
- unsigned char mode;
-} tx4939irq[TX4939_NUM_IR] __read_mostly;
-
-static void tx4939_irq_unmask(struct irq_data *d)
-{
- unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
- u32 __iomem *lvlp;
- int ofs;
- if (irq_nr < 32) {
- irq_nr--;
- lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
- } else {
- irq_nr -= 32;
- lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
- }
- ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
- __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
- | (tx4939irq[irq_nr].level << ofs),
- lvlp);
-}
-
-static inline void tx4939_irq_mask(struct irq_data *d)
-{
- unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
- u32 __iomem *lvlp;
- int ofs;
- if (irq_nr < 32) {
- irq_nr--;
- lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
- } else {
- irq_nr -= 32;
- lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
- }
- ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
- __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
- | (irc_dlevel << ofs),
- lvlp);
- mmiowb();
-}
-
-static void tx4939_irq_mask_ack(struct irq_data *d)
-{
- unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
-
- tx4939_irq_mask(d);
- if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
- irq_nr--;
- /* clear edge detection */
- __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
- << (irq_nr & 0x10),
- &tx4939_ircptr->edc.r);
- }
-}
-
-static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
- unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
- u32 cr;
- u32 __iomem *crp;
- int ofs;
- int mode;
-
- if (flow_type & IRQF_TRIGGER_PROBE)
- return 0;
- switch (flow_type & IRQF_TRIGGER_MASK) {
- case IRQF_TRIGGER_RISING:
- mode = TXx9_IRCR_UP;
- break;
- case IRQF_TRIGGER_FALLING:
- mode = TXx9_IRCR_DOWN;
- break;
- case IRQF_TRIGGER_HIGH:
- mode = TXx9_IRCR_HIGH;
- break;
- case IRQF_TRIGGER_LOW:
- mode = TXx9_IRCR_LOW;
- break;
- default:
- return -EINVAL;
- }
- if (irq_nr < 32) {
- irq_nr--;
- crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
- } else {
- irq_nr -= 32;
- crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
- }
- ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
- cr = __raw_readl(crp);
- cr &= ~(0x3 << ofs);
- cr |= (mode & 0x3) << ofs;
- __raw_writel(cr, crp);
- tx4939irq[irq_nr].mode = mode;
- return 0;
-}
-
-static struct irq_chip tx4939_irq_chip = {
- .name = "TX4939",
- .irq_ack = tx4939_irq_mask_ack,
- .irq_mask = tx4939_irq_mask,
- .irq_mask_ack = tx4939_irq_mask_ack,
- .irq_unmask = tx4939_irq_unmask,
- .irq_set_type = tx4939_irq_set_type,
-};
-
-static int tx4939_irq_set_pri(int irc_irq, int new_pri)
-{
- int old_pri;
-
- if ((unsigned int)irc_irq >= TX4939_NUM_IR)
- return 0;
- old_pri = tx4939irq[irc_irq].level;
- tx4939irq[irc_irq].level = new_pri;
- return old_pri;
-}
-
-void __init tx4939_irq_init(void)
-{
- int i;
-
- mips_cpu_irq_init();
- /* disable interrupt control */
- __raw_writel(0, &tx4939_ircptr->den.r);
- __raw_writel(0, &tx4939_ircptr->maskint.r);
- __raw_writel(0, &tx4939_ircptr->maskext.r);
- /* irq_base + 0 is not used */
- for (i = 1; i < TX4939_NUM_IR; i++) {
- tx4939irq[i].level = 4; /* middle level */
- tx4939irq[i].mode = TXx9_IRCR_LOW;
- irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
- handle_level_irq);
- }
-
- /* mask all IRC interrupts */
- __raw_writel(0, &tx4939_ircptr->msk.r);
- for (i = 0; i < 16; i++)
- __raw_writel(0, &tx4939_ircptr->lvl[i].r);
- /* setup IRC interrupt mode (Low Active) */
- for (i = 0; i < 2; i++)
- __raw_writel(0, &tx4939_ircptr->dm[i].r);
- for (i = 0; i < 2; i++)
- __raw_writel(0, &tx4939_ircptr->dm2[i].r);
- /* enable interrupt control */
- __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
- __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
-
- irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
- handle_simple_irq);
-
- /* raise priority for errors, timers, sio */
- tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
- tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
- tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
- for (i = 0; i < TX4939_NUM_IR_TMR; i++)
- tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
- for (i = 0; i < TX4939_NUM_IR_SIO; i++)
- tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
-}
-
-int tx4939_irq(void)
-{
- u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
-
- if (likely(!(csr & TXx9_IRCSR_IF)))
- return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
- return -1;
-}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 42ba1e97dff0..39cd1edf9d80 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -314,16 +314,6 @@ static void __init select_board(void)
case 0x4937:
txx9_board_vec = &rbtx4937_vec;
break;
-#endif
-#ifdef CONFIG_TOSHIBA_RBTX4938
- case 0x4938:
- txx9_board_vec = &rbtx4938_vec;
- break;
-#endif
-#ifdef CONFIG_TOSHIBA_RBTX4939
- case 0x4939:
- txx9_board_vec = &rbtx4939_vec;
- break;
#endif
}
#endif
@@ -590,21 +580,6 @@ unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
EXPORT_SYMBOL(__swizzle_addr_b);
#endif
-#ifdef NEEDS_TXX9_IOSWABW
-static u16 ioswabw_default(volatile u16 *a, u16 x)
-{
- return le16_to_cpu(x);
-}
-static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
-{
- return x;
-}
-u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
-EXPORT_SYMBOL(ioswabw);
-u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
-EXPORT_SYMBOL(__mem_ioswabw);
-#endif
-
void __init txx9_physmap_flash_init(int no, unsigned long addr,
unsigned long size,
const struct physmap_flash_data *pdata)
@@ -840,34 +815,6 @@ void __init txx9_aclc_init(unsigned long baseaddr, int irq,
unsigned int dma_chan_out,
unsigned int dma_chan_in)
{
-#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
- unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
- struct resource res[] = {
- {
- .start = baseaddr,
- .end = baseaddr + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = irq,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "txx9dmac-chan",
- .start = dma_base + dma_chan_out,
- .flags = IORESOURCE_DMA,
- }, {
- .name = "txx9dmac-chan",
- .start = dma_base + dma_chan_in,
- .flags = IORESOURCE_DMA,
- }
- };
- struct platform_device *pdev =
- platform_device_alloc("txx9aclc-ac97", -1);
-
- if (!pdev ||
- platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
- platform_device_add(pdev))
- platform_device_put(pdev);
-#endif
}
static struct bus_type txx9_sramc_subsys = {
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
deleted file mode 100644
index f5f59b7401a3..000000000000
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ /dev/null
@@ -1,568 +0,0 @@
-/*
- * TX4939 setup routines
- * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
- * and RBTX49xx patch from CELF patch archive.
- *
- * 2003-2005 (c) MontaVista Software, Inc.
- * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/notifier.h>
-#include <linux/device.h>
-#include <linux/ethtool.h>
-#include <linux/param.h>
-#include <linux/ptrace.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/txx9/ndfmc.h>
-#include <asm/reboot.h>
-#include <asm/traps.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9tmr.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/dmac.h>
-#include <asm/txx9/tx4939.h>
-
-static void __init tx4939_wdr_init(void)
-{
- /* report watchdog reset status */
- if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
- pr_warn("Watchdog reset detected at 0x%lx\n",
- read_c0_errorepc());
- /* clear WatchDogReset (W1C) */
- tx4939_ccfg_set(TX4939_CCFG_WDRST);
- /* do reset on watchdog */
- tx4939_ccfg_set(TX4939_CCFG_WR);
-}
-
-void __init tx4939_wdt_init(void)
-{
- txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
-}
-
-static void tx4939_machine_restart(char *command)
-{
- local_irq_disable();
- pr_emerg("Rebooting (with %s watchdog reset)...\n",
- (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
- "external" : "internal");
- /* clear watchdog status */
- tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
- txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
- while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
- ;
- mdelay(10);
- if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
- pr_emerg("Rebooting (with internal watchdog reset)...\n");
- /* External WDRST failed. Do internal watchdog reset */
- tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
- }
- /* fallback */
- (*_machine_halt)();
-}
-
-void show_registers(struct pt_regs *regs);
-static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
-{
- int data = regs->cp0_cause & 4;
- console_verbose();
- pr_err("%cBE exception at %#lx\n",
- data ? 'D' : 'I', regs->cp0_epc);
- pr_err("ccfg:%llx, toea:%llx\n",
- (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
- (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
-#ifdef CONFIG_PCI
- tx4927_report_pcic_status();
-#endif
- show_registers(regs);
- panic("BusError!");
-}
-static void __init tx4939_be_init(void)
-{
- mips_set_be_handler(tx4939_be_handler);
-}
-
-static struct resource tx4939_sdram_resource[4];
-static struct resource tx4939_sram_resource;
-#define TX4939_SRAM_SIZE 0x800
-
-void __init tx4939_setup(void)
-{
- int i;
- __u32 divmode;
- __u64 pcfg;
- unsigned int cpuclk = 0;
-
- txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
- TX4939_REG_SIZE);
- set_c0_config(TX49_CONF_CWFON);
-
- /* SDRAMC,EBUSC are configured by PROM */
- for (i = 0; i < 4; i++) {
- if (!(TX4939_EBUSC_CR(i) & 0x8))
- continue; /* disabled */
- txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
- txx9_ce_res[i].end =
- txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
- request_resource(&iomem_resource, &txx9_ce_res[i]);
- }
-
- /* clocks */
- if (txx9_master_clock) {
- /* calculate cpu_clock from master_clock */
- divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
- TX4939_CCFG_MULCLK_MASK;
- cpuclk = txx9_master_clock * 20 / 2;
- switch (divmode) {
- case TX4939_CCFG_MULCLK_8:
- cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
- case TX4939_CCFG_MULCLK_9:
- cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
- case TX4939_CCFG_MULCLK_10:
- cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
- case TX4939_CCFG_MULCLK_11:
- cpuclk = cpuclk / 6 * 11; break;
- case TX4939_CCFG_MULCLK_12:
- cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
- case TX4939_CCFG_MULCLK_13:
- cpuclk = cpuclk / 6 * 13; break;
- case TX4939_CCFG_MULCLK_14:
- cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
- case TX4939_CCFG_MULCLK_15:
- cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
- }
- txx9_cpu_clock = cpuclk;
- } else {
- if (txx9_cpu_clock == 0)
- txx9_cpu_clock = 400000000; /* 400MHz */
- /* calculate master_clock from cpu_clock */
- cpuclk = txx9_cpu_clock;
- divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
- TX4939_CCFG_MULCLK_MASK;
- switch (divmode) {
- case TX4939_CCFG_MULCLK_8:
- txx9_master_clock = cpuclk * 6 / 8; break;
- case TX4939_CCFG_MULCLK_9:
- txx9_master_clock = cpuclk * 6 / 9; break;
- case TX4939_CCFG_MULCLK_10:
- txx9_master_clock = cpuclk * 6 / 10; break;
- case TX4939_CCFG_MULCLK_11:
- txx9_master_clock = cpuclk * 6 / 11; break;
- case TX4939_CCFG_MULCLK_12:
- txx9_master_clock = cpuclk * 6 / 12; break;
- case TX4939_CCFG_MULCLK_13:
- txx9_master_clock = cpuclk * 6 / 13; break;
- case TX4939_CCFG_MULCLK_14:
- txx9_master_clock = cpuclk * 6 / 14; break;
- case TX4939_CCFG_MULCLK_15:
- txx9_master_clock = cpuclk * 6 / 15; break;
- }
- txx9_master_clock /= 10; /* * 2 / 20 */
- }
- /* calculate gbus_clock from cpu_clock */
- divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
- TX4939_CCFG_YDIVMODE_MASK;
- txx9_gbus_clock = txx9_cpu_clock;
- switch (divmode) {
- case TX4939_CCFG_YDIVMODE_2:
- txx9_gbus_clock /= 2; break;
- case TX4939_CCFG_YDIVMODE_3:
- txx9_gbus_clock /= 3; break;
- case TX4939_CCFG_YDIVMODE_5:
- txx9_gbus_clock /= 5; break;
- case TX4939_CCFG_YDIVMODE_6:
- txx9_gbus_clock /= 6; break;
- }
- /* change default value to udelay/mdelay take reasonable time */
- loops_per_jiffy = txx9_cpu_clock / HZ / 2;
-
- /* CCFG */
- tx4939_wdr_init();
- /* clear BusErrorOnWrite flag (W1C) */
- tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
- /* enable Timeout BusError */
- if (txx9_ccfg_toeon)
- tx4939_ccfg_set(TX4939_CCFG_TOE);
-
- /* DMA selection */
- txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
-
- /* Use external clock for external arbiter */
- if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
- txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
-
- pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
- txx9_pcode_str,
- (cpuclk + 500000) / 1000000,
- (txx9_master_clock + 500000) / 1000000,
- (txx9_gbus_clock + 500000) / 1000000,
- (__u32)____raw_readq(&tx4939_ccfgptr->crir),
- ____raw_readq(&tx4939_ccfgptr->ccfg),
- ____raw_readq(&tx4939_ccfgptr->pcfg));
-
- pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
- (__u32)____raw_readq(&tx4939_ddrcptr->winen));
- for (i = 0; i < 4; i++) {
- __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
- if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
- continue; /* disabled */
- pr_cont(" #%d:%016llx", i, win);
- tx4939_sdram_resource[i].name = "DDR SDRAM";
- tx4939_sdram_resource[i].start =
- (unsigned long)(win >> 48) << 20;
- tx4939_sdram_resource[i].end =
- ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
- 20) - 1;
- tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
- request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
- }
- pr_cont("\n");
-
- /* SRAM */
- if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
- unsigned int size = TX4939_SRAM_SIZE;
- tx4939_sram_resource.name = "SRAM";
- tx4939_sram_resource.start =
- (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
- & ~(size - 1);
- tx4939_sram_resource.end =
- tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
- tx4939_sram_resource.flags = IORESOURCE_MEM;
- request_resource(&iomem_resource, &tx4939_sram_resource);
- }
-
- /* TMR */
- /* disable all timers */
- for (i = 0; i < TX4939_NR_TMR; i++)
- txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
-
- /* set PCIC1 reset (required to prevent hangup on BIST) */
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
- pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
- if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
- mdelay(1); /* at least 128 cpu clock */
- /* clear PCIC1 reset */
- txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
- } else {
- pr_info("%s: stop PCIC1\n", txx9_pcode_str);
- /* stop PCIC1 */
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
- }
- if (!(pcfg & TX4939_PCFG_ET0MODE)) {
- pr_info("%s: stop ETH0\n", txx9_pcode_str);
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
- }
- if (!(pcfg & TX4939_PCFG_ET1MODE)) {
- pr_info("%s: stop ETH1\n", txx9_pcode_str);
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
- txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
- }
-
- _machine_restart = tx4939_machine_restart;
- board_be_init = tx4939_be_init;
-}
-
-void __init tx4939_time_init(unsigned int tmrnr)
-{
- if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
- txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
- TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
- TXX9_IMCLK);
-}
-
-void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
-{
- int i;
- unsigned int ch_mask = 0;
- __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
-
- cts_mask |= ~1; /* only SIO0 have RTS/CTS */
- if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
- cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
- if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
- ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
- if (pcfg & TX4939_PCFG_SIO3MODE)
- ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
- for (i = 0; i < 4; i++) {
- if ((1 << i) & ch_mask)
- continue;
- txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
- TXX9_IRQ_BASE + TX4939_IR_SIO(i),
- i, sclk, (1 << i) & cts_mask);
- }
-}
-
-#if IS_ENABLED(CONFIG_TC35815)
-static u32 tx4939_get_eth_speed(struct net_device *dev)
-{
- struct ethtool_link_ksettings cmd;
-
- if (__ethtool_get_link_ksettings(dev, &cmd))
- return 100; /* default 100Mbps */
-
- return cmd.base.speed;
-}
-
-static int tx4939_netdev_event(struct notifier_block *this,
- unsigned long event,
- void *ptr)
-{
- struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-
- if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
- __u64 bit = 0;
- if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
- bit = TX4939_PCFG_SPEED0;
- else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
- bit = TX4939_PCFG_SPEED1;
- if (bit) {
- if (tx4939_get_eth_speed(dev) == 100)
- txx9_set64(&tx4939_ccfgptr->pcfg, bit);
- else
- txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
- }
- }
- return NOTIFY_DONE;
-}
-
-static struct notifier_block tx4939_netdev_notifier = {
- .notifier_call = tx4939_netdev_event,
- .priority = 1,
-};
-
-void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
-{
- u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
-
- if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
- txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
- if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
- txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
- register_netdevice_notifier(&tx4939_netdev_notifier);
-}
-#else
-void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
-{
-}
-#endif
-
-void __init tx4939_mtd_init(int ch)
-{
- struct physmap_flash_data pdata = {
- .width = TX4939_EBUSC_WIDTH(ch) / 8,
- };
- unsigned long start = txx9_ce_res[ch].start;
- unsigned long size = txx9_ce_res[ch].end - start + 1;
-
- if (!(TX4939_EBUSC_CR(ch) & 0x8))
- return; /* disabled */
- txx9_physmap_flash_init(ch, start, size, &pdata);
-}
-
-#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
-void __init tx4939_ata_init(void)
-{
- static struct resource ata0_res[] = {
- {
- .start = TX4939_ATA_REG_PHYS(0),
- .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
- .flags = IORESOURCE_IRQ,
- },
- };
- static struct resource ata1_res[] = {
- {
- .start = TX4939_ATA_REG_PHYS(1),
- .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
- .flags = IORESOURCE_IRQ,
- },
- };
- static struct platform_device ata0_dev = {
- .name = "tx4939ide",
- .id = 0,
- .num_resources = ARRAY_SIZE(ata0_res),
- .resource = ata0_res,
- };
- static struct platform_device ata1_dev = {
- .name = "tx4939ide",
- .id = 1,
- .num_resources = ARRAY_SIZE(ata1_res),
- .resource = ata1_res,
- };
- __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
-
- if (pcfg & TX4939_PCFG_ATA0MODE)
- platform_device_register(&ata0_dev);
- if ((pcfg & (TX4939_PCFG_ATA1MODE |
- TX4939_PCFG_ET1MODE |
- TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
- platform_device_register(&ata1_dev);
-}
-
-void __init tx4939_rtc_init(void)
-{
- static struct resource res[] = {
- {
- .start = TX4939_RTC_REG & 0xfffffffffULL,
- .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
- .flags = IORESOURCE_IRQ,
- },
- };
- static struct platform_device rtc_dev = {
- .name = "tx4939rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(res),
- .resource = res,
- };
-
- platform_device_register(&rtc_dev);
-}
-
-void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
- unsigned char ch_mask, unsigned char wide_mask)
-{
- struct txx9ndfmc_platform_data plat_data = {
- .shift = 1,
- .gbus_clock = txx9_gbus_clock,
- .hold = hold,
- .spw = spw,
- .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
- NDFMC_PLAT_FLAG_DUMMYWRITE,
- .ch_mask = ch_mask,
- .wide_mask = wide_mask,
- };
- txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
-}
-
-void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
-{
- struct txx9dmac_platform_data plat_data = {
- .have_64bit_regs = true,
- };
- int i;
-
- for (i = 0; i < 2; i++) {
- plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
- txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
- TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
- &plat_data);
- }
-}
-
-void __init tx4939_aclc_init(void)
-{
- u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
-
- if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
- txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
- TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
-}
-
-void __init tx4939_sramc_init(void)
-{
- if (tx4939_sram_resource.start)
- txx9_sramc_init(&tx4939_sram_resource);
-}
-
-void __init tx4939_rng_init(void)
-{
- static struct resource res = {
- .start = TX4939_RNG_REG & 0xfffffffffULL,
- .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
- .flags = IORESOURCE_MEM,
- };
- static struct platform_device pdev = {
- .name = "tx4939-rng",
- .id = -1,
- .num_resources = 1,
- .resource = &res,
- };
-
- platform_device_register(&pdev);
-}
-
-static void __init tx4939_stop_unused_modules(void)
-{
- __u64 pcfg, rst = 0, ckd = 0;
- char buf[128];
-
- buf[0] = '\0';
- local_irq_disable();
- pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
- if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
- TX4939_PCFG_I2SMODE_ACLC) {
- rst |= TX4939_CLKCTR_ACLRST;
- ckd |= TX4939_CLKCTR_ACLCKD;
- strcat(buf, " ACLC");
- }
- if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
- TX4939_PCFG_I2SMODE_I2S &&
- (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
- TX4939_PCFG_I2SMODE_I2S_ALT) {
- rst |= TX4939_CLKCTR_I2SRST;
- ckd |= TX4939_CLKCTR_I2SCKD;
- strcat(buf, " I2S");
- }
- if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
- rst |= TX4939_CLKCTR_ATA0RST;
- ckd |= TX4939_CLKCTR_ATA0CKD;
- strcat(buf, " ATA0");
- }
- if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
- rst |= TX4939_CLKCTR_ATA1RST;
- ckd |= TX4939_CLKCTR_ATA1CKD;
- strcat(buf, " ATA1");
- }
- if (pcfg & TX4939_PCFG_SPIMODE) {
- rst |= TX4939_CLKCTR_SPIRST;
- ckd |= TX4939_CLKCTR_SPICKD;
- strcat(buf, " SPI");
- }
- if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
- rst |= TX4939_CLKCTR_VPCRST;
- ckd |= TX4939_CLKCTR_VPCCKD;
- strcat(buf, " VPC");
- }
- if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
- rst |= TX4939_CLKCTR_SIO2RST;
- ckd |= TX4939_CLKCTR_SIO2CKD;
- strcat(buf, " SIO2");
- }
- if (pcfg & TX4939_PCFG_SIO3MODE) {
- rst |= TX4939_CLKCTR_SIO3RST;
- ckd |= TX4939_CLKCTR_SIO3CKD;
- strcat(buf, " SIO3");
- }
- if (rst | ckd) {
- txx9_set64(&tx4939_ccfgptr->clkctr, rst);
- txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
- }
- local_irq_enable();
- if (buf[0])
- pr_info("%s: stop%s\n", txx9_pcode_str, buf);
-}
-
-static int __init tx4939_late_init(void)
-{
- if (txx9_pcode != 0x4939)
- return -ENODEV;
- tx4939_stop_unused_modules();
- return 0;
-}
-late_initcall(tx4939_late_init);
diff --git a/arch/mips/txx9/generic/spi_eeprom.c b/arch/mips/txx9/generic/spi_eeprom.c
deleted file mode 100644
index d833dd2c9b55..000000000000
--- a/arch/mips/txx9/generic/spi_eeprom.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * spi_eeprom.c
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <asm/txx9/spi.h>
-
-#define AT250X0_PAGE_SIZE 8
-
-/* register board information for at25 driver */
-int __init spi_eeprom_register(int busid, int chipid, int size)
-{
- struct spi_board_info info = {
- .modalias = "at25",
- .max_speed_hz = 1500000, /* 1.5Mbps */
- .bus_num = busid,
- .chip_select = chipid,
- /* Mode 0: High-Active, Sample-Then-Shift */
- };
- struct spi_eeprom *eeprom;
- eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
- if (!eeprom)
- return -ENOMEM;
- strcpy(eeprom->name, "at250x0");
- eeprom->byte_len = size;
- eeprom->page_size = AT250X0_PAGE_SIZE;
- eeprom->flags = EE_ADDR1;
- info.platform_data = eeprom;
- return spi_register_board_info(&info, 1);
-}
-
-/* simple temporary spi driver to provide early access to seeprom. */
-
-static struct read_param {
- int busid;
- int chipid;
- int address;
- unsigned char *buf;
- int len;
-} *read_param;
-
-static int __init early_seeprom_probe(struct spi_device *spi)
-{
- int stat = 0;
- u8 cmd[2];
- int len = read_param->len;
- char *buf = read_param->buf;
- int address = read_param->address;
-
- dev_info(&spi->dev, "spiclk %u KHz.\n",
- (spi->max_speed_hz + 500) / 1000);
- if (read_param->busid != spi->master->bus_num ||
- read_param->chipid != spi->chip_select)
- return -ENODEV;
- while (len > 0) {
- /* spi_write_then_read can only work with small chunk */
- int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
- cmd[0] = 0x03; /* AT25_READ */
- cmd[1] = address;
- stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
- buf += c;
- len -= c;
- address += c;
- }
- return stat;
-}
-
-static struct spi_driver early_seeprom_driver __initdata = {
- .driver = {
- .name = "at25",
- },
- .probe = early_seeprom_probe,
-};
-
-int __init spi_eeprom_read(int busid, int chipid, int address,
- unsigned char *buf, int len)
-{
- int ret;
- struct read_param param = {
- .busid = busid,
- .chipid = chipid,
- .address = address,
- .buf = buf,
- .len = len
- };
-
- read_param = ¶m;
- ret = spi_register_driver(&early_seeprom_driver);
- if (!ret)
- spi_unregister_driver(&early_seeprom_driver);
- return ret;
-}
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
deleted file mode 100644
index 08a02aebda5a..000000000000
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += prom.o setup.o irq.o
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
deleted file mode 100644
index 58cd7a9272cc..000000000000
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Toshiba RBTX4938 specific interrupt handlers
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-
-/*
- * MIPS_CPU_IRQ_BASE+00 Software 0
- * MIPS_CPU_IRQ_BASE+01 Software 1
- * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
- * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
- * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
- * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
- * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
- * MIPS_CPU_IRQ_BASE+07 CPU TIMER
- *
- * TXX9_IRQ_BASE+00
- * TXX9_IRQ_BASE+01
- * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
- * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
- * TXX9_IRQ_BASE+04
- * TXX9_IRQ_BASE+05 TX4938 ETH1
- * TXX9_IRQ_BASE+06 TX4938 ETH0
- * TXX9_IRQ_BASE+07
- * TXX9_IRQ_BASE+08 TX4938 SIO 0
- * TXX9_IRQ_BASE+09 TX4938 SIO 1
- * TXX9_IRQ_BASE+10 TX4938 DMA0
- * TXX9_IRQ_BASE+11 TX4938 DMA1
- * TXX9_IRQ_BASE+12 TX4938 DMA2
- * TXX9_IRQ_BASE+13 TX4938 DMA3
- * TXX9_IRQ_BASE+14
- * TXX9_IRQ_BASE+15
- * TXX9_IRQ_BASE+16 TX4938 PCIC
- * TXX9_IRQ_BASE+17 TX4938 TMR0
- * TXX9_IRQ_BASE+18 TX4938 TMR1
- * TXX9_IRQ_BASE+19 TX4938 TMR2
- * TXX9_IRQ_BASE+20
- * TXX9_IRQ_BASE+21
- * TXX9_IRQ_BASE+22 TX4938 PCIERR
- * TXX9_IRQ_BASE+23
- * TXX9_IRQ_BASE+24
- * TXX9_IRQ_BASE+25
- * TXX9_IRQ_BASE+26
- * TXX9_IRQ_BASE+27
- * TXX9_IRQ_BASE+28
- * TXX9_IRQ_BASE+29
- * TXX9_IRQ_BASE+30
- * TXX9_IRQ_BASE+31 TX4938 SPI
- *
- * RBTX4938_IRQ_IOC+00 PCI-D
- * RBTX4938_IRQ_IOC+01 PCI-C
- * RBTX4938_IRQ_IOC+02 PCI-B
- * RBTX4938_IRQ_IOC+03 PCI-A
- * RBTX4938_IRQ_IOC+04 RTC
- * RBTX4938_IRQ_IOC+05 ATA
- * RBTX4938_IRQ_IOC+06 MODEM
- * RBTX4938_IRQ_IOC+07 SWINT
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/rbtx4938.h>
-
-static int toshiba_rbtx4938_irq_nested(int sw_irq)
-{
- u8 level3;
-
- level3 = readb(rbtx4938_imstat_addr);
- if (unlikely(!level3))
- return -1;
- /* must use fls so onboard ATA has priority */
- return RBTX4938_IRQ_IOC + __fls8(level3);
-}
-
-static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
-{
- unsigned char v;
-
- v = readb(rbtx4938_imask_addr);
- v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
- writeb(v, rbtx4938_imask_addr);
- mmiowb();
-}
-
-static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
-{
- unsigned char v;
-
- v = readb(rbtx4938_imask_addr);
- v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
- writeb(v, rbtx4938_imask_addr);
- mmiowb();
-}
-
-#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
-static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
- .name = TOSHIBA_RBTX4938_IOC_NAME,
- .irq_mask = toshiba_rbtx4938_irq_ioc_disable,
- .irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
-};
-
-static int rbtx4938_irq_dispatch(int pending)
-{
- int irq;
-
- if (pending & STATUSF_IP7)
- irq = MIPS_CPU_IRQ_BASE + 7;
- else if (pending & STATUSF_IP2) {
- irq = txx9_irq();
- if (irq == RBTX4938_IRQ_IOCINT)
- irq = toshiba_rbtx4938_irq_nested(irq);
- } else if (pending & STATUSF_IP1)
- irq = MIPS_CPU_IRQ_BASE + 0;
- else if (pending & STATUSF_IP0)
- irq = MIPS_CPU_IRQ_BASE + 1;
- else
- irq = -1;
- return irq;
-}
-
-static void __init toshiba_rbtx4938_irq_ioc_init(void)
-{
- int i;
-
- for (i = RBTX4938_IRQ_IOC;
- i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
- irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
- handle_level_irq);
-
- irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
-}
-
-void __init rbtx4938_irq_setup(void)
-{
- txx9_irq_dispatch = rbtx4938_irq_dispatch;
- /* Now, interrupt control disabled, */
- /* all IRC interrupts are masked, */
- /* all IRC interrupt mode are Low Active. */
-
- /* mask all IOC interrupts */
- writeb(0, rbtx4938_imask_addr);
-
- /* clear SoftInt interrupts */
- writeb(0, rbtx4938_softint_addr);
- tx4938_irq_init();
- toshiba_rbtx4938_irq_ioc_init();
- /* Onboard 10M Ether: High Active */
- irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
-}
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
deleted file mode 100644
index 0de84716a428..000000000000
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * rbtx4938 specific prom routines
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/rbtx4938.h>
-
-void __init rbtx4938_prom_init(void)
-{
- memblock_add(0, tx4938_get_mem_size());
- txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
-}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
deleted file mode 100644
index e68eb2e7ce0c..000000000000
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * Setup pointers to hardware-dependent routines.
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/reboot.h>
-#include <asm/io.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/pci.h>
-#include <asm/txx9/rbtx4938.h>
-#include <linux/spi/spi.h>
-#include <asm/txx9/spi.h>
-#include <asm/txx9pio.h>
-
-static void rbtx4938_machine_restart(char *command)
-{
- local_irq_disable();
- writeb(1, rbtx4938_softresetlock_addr);
- writeb(1, rbtx4938_sfvol_addr);
- writeb(1, rbtx4938_softreset_addr);
- /* fallback */
- (*_machine_halt)();
-}
-
-static void __init rbtx4938_pci_setup(void)
-{
-#ifdef CONFIG_PCI
- int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
- struct pci_controller *c = &txx9_primary_pcic;
-
- register_pci_controller(c);
-
- if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
- txx9_pci_option =
- (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
- TXX9_PCI_OPT_CLK_66; /* already configured */
-
- /* Reset PCI Bus */
- writeb(0, rbtx4938_pcireset_addr);
- /* Reset PCIC */
- txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
- if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
- TXX9_PCI_OPT_CLK_66)
- tx4938_pciclk66_setup();
- mdelay(10);
- /* clear PCIC reset */
- txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
- writeb(1, rbtx4938_pcireset_addr);
- iob();
-
- tx4938_report_pciclk();
- tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
- if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
- TXX9_PCI_OPT_CLK_AUTO &&
- txx9_pci66_check(c, 0, 0)) {
- /* Reset PCI Bus */
- writeb(0, rbtx4938_pcireset_addr);
- /* Reset PCIC */
- txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
- tx4938_pciclk66_setup();
- mdelay(10);
- /* clear PCIC reset */
- txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
- writeb(1, rbtx4938_pcireset_addr);
- iob();
- /* Reinitialize PCIC */
- tx4938_report_pciclk();
- tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
- }
-
- if (__raw_readq(&tx4938_ccfgptr->pcfg) &
- (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
- /* Reset PCIC1 */
- txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
- /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
- if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
- & TX4938_CCFG_PCI1DMD))
- tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
- mdelay(10);
- /* clear PCIC1 reset */
- txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
- tx4938_report_pci1clk();
-
- /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
- c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
- register_pci_controller(c);
- tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
- }
- tx4938_setup_pcierr_irq();
-#endif /* CONFIG_PCI */
-}
-
-/* SPI support */
-
-/* chip select for SPI devices */
-#define SEEPROM1_CS 7 /* PIO7 */
-#define SEEPROM2_CS 0 /* IOC */
-#define SEEPROM3_CS 1 /* IOC */
-#define SRTC_CS 2 /* IOC */
-#define SPI_BUSNO 0
-
-static int __init rbtx4938_ethaddr_init(void)
-{
-#ifdef CONFIG_PCI
- unsigned char dat[17];
- unsigned char sum;
- int i;
-
- /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
- if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
- pr_err("seeprom: read error.\n");
- return -ENODEV;
- } else {
- if (strcmp(dat, "MAC") != 0)
- pr_warn("seeprom: bad signature.\n");
- for (i = 0, sum = 0; i < sizeof(dat); i++)
- sum += dat[i];
- if (sum)
- pr_warn("seeprom: bad checksum.\n");
- }
- tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
-#endif /* CONFIG_PCI */
- return 0;
-}
-
-static void __init rbtx4938_spi_setup(void)
-{
- /* set SPI_SEL */
- txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
-}
-
-static struct resource rbtx4938_fpga_resource;
-
-static void __init rbtx4938_time_init(void)
-{
- tx4938_time_init(0);
-}
-
-static void __init rbtx4938_mem_setup(void)
-{
- unsigned long long pcfg;
-
- if (txx9_master_clock == 0)
- txx9_master_clock = 25000000; /* 25MHz */
-
- tx4938_setup();
-
-#ifdef CONFIG_PCI
- txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
- txx9_board_pcibios_setup = tx4927_pcibios_setup;
-#else
- set_io_port_base(RBTX4938_ETHER_BASE);
-#endif
-
- tx4938_sio_init(7372800, 0);
-
-#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
- pr_info("PIOSEL: disabling both ATA and NAND selection\n");
- txx9_clear64(&tx4938_ccfgptr->pcfg,
- TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
-#endif
-
-#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
- pr_info("PIOSEL: enabling NAND selection\n");
- txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
- txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
-#endif
-
-#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
- pr_info("PIOSEL: enabling ATA selection\n");
- txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
- txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
-#endif
-
-#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
- pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
- pr_info("PIOSEL: NAND %s, ATA %s\n",
- (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
- (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
-#endif
-
- rbtx4938_spi_setup();
- pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
- /* fixup piosel */
- if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
- TX4938_PCFG_ATA_SEL)
- writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
- rbtx4938_piosel_addr);
- else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
- TX4938_PCFG_NDF_SEL)
- writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
- rbtx4938_piosel_addr);
- else
- writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
- rbtx4938_piosel_addr);
-
- rbtx4938_fpga_resource.name = "FPGA Registers";
- rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
- rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
- rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
- if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
- pr_err("request resource for fpga failed\n");
-
- _machine_restart = rbtx4938_machine_restart;
-
- writeb(0xff, rbtx4938_led_addr);
- pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
- readb(rbtx4938_fpga_rev_addr),
- readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
-}
-
-static void __init rbtx4938_ne_init(void)
-{
- struct resource res[] = {
- {
- .start = RBTX4938_RTL_8019_BASE,
- .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
- .flags = IORESOURCE_IO,
- }, {
- .start = RBTX4938_RTL_8019_IRQ,
- .flags = IORESOURCE_IRQ,
- }
- };
- platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
-}
-
-static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
-
-static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
- int value)
-{
- u8 val;
- unsigned long flags;
- spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
- val = readb(rbtx4938_spics_addr);
- if (value)
- val |= 1 << offset;
- else
- val &= ~(1 << offset);
- writeb(val, rbtx4938_spics_addr);
- mmiowb();
- spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
-}
-
-static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
- unsigned int offset, int value)
-{
- rbtx4938_spi_gpio_set(chip, offset, value);
- return 0;
-}
-
-static struct gpio_chip rbtx4938_spi_gpio_chip = {
- .set = rbtx4938_spi_gpio_set,
- .direction_output = rbtx4938_spi_gpio_dir_out,
- .label = "RBTX4938-SPICS",
- .base = 16,
- .ngpio = 3,
-};
-
-static int __init rbtx4938_spi_init(void)
-{
- struct spi_board_info srtc_info = {
- .modalias = "rtc-rs5c348",
- .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
- .bus_num = 0,
- .chip_select = 16 + SRTC_CS,
- /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
- .mode = SPI_MODE_1 | SPI_CS_HIGH,
- };
- spi_register_board_info(&srtc_info, 1);
- spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
- spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
- spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
- gpio_request(16 + SRTC_CS, "rtc-rs5c348");
- gpio_direction_output(16 + SRTC_CS, 0);
- gpio_request(SEEPROM1_CS, "seeprom1");
- gpio_direction_output(SEEPROM1_CS, 1);
- gpio_request(16 + SEEPROM2_CS, "seeprom2");
- gpio_direction_output(16 + SEEPROM2_CS, 1);
- gpio_request(16 + SEEPROM3_CS, "seeprom3");
- gpio_direction_output(16 + SEEPROM3_CS, 1);
- tx4938_spi_init(SPI_BUSNO);
- return 0;
-}
-
-static void __init rbtx4938_mtd_init(void)
-{
- struct physmap_flash_data pdata = {
- .width = 4,
- };
-
- switch (readb(rbtx4938_bdipsw_addr) & 7) {
- case 0:
- /* Boot */
- txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
- /* System */
- txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
- break;
- case 1:
- /* System */
- txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
- /* Boot */
- txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
- break;
- case 2:
- /* Ext */
- txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
- /* System */
- txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
- /* Boot */
- txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
- break;
- case 3:
- /* Boot */
- txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
- /* System */
- txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
- break;
- }
-}
-
-static void __init rbtx4938_arch_init(void)
-{
- txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
- gpiochip_add_data(&rbtx4938_spi_gpio_chip, NULL);
- rbtx4938_pci_setup();
- rbtx4938_spi_init();
-}
-
-static void __init rbtx4938_device_init(void)
-{
- rbtx4938_ethaddr_init();
- rbtx4938_ne_init();
- tx4938_wdt_init();
- rbtx4938_mtd_init();
- /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
- tx4938_ndfmc_init(10, 35);
- tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
- tx4938_dmac_init(0, 2);
- tx4938_aclc_init();
- platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
- tx4938_sramc_init();
- txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
-}
-
-struct txx9_board_vec rbtx4938_vec __initdata = {
- .system = "Toshiba RBTX4938",
- .prom_init = rbtx4938_prom_init,
- .mem_setup = rbtx4938_mem_setup,
- .irq_setup = rbtx4938_irq_setup,
- .time_init = rbtx4938_time_init,
- .device_init = rbtx4938_device_init,
- .arch_init = rbtx4938_arch_init,
-#ifdef CONFIG_PCI
- .pci_map_irq = rbtx4938_pci_map_irq,
-#endif
-};
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
deleted file mode 100644
index 840496e7a76e..000000000000
--- a/arch/mips/txx9/rbtx4939/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += irq.o setup.o prom.o
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
deleted file mode 100644
index 69a80616f0c9..000000000000
--- a/arch/mips/txx9/rbtx4939/irq.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Toshiba RBTX4939 interrupt routines
- * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
- * and RBTX49xx patch from CELF patch archive.
- *
- * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/txx9/rbtx4939.h>
-
-/*
- * RBTX4939 IOC controller definition
- */
-
-static void rbtx4939_ioc_irq_unmask(struct irq_data *d)
-{
- int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
-
- writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
-}
-
-static void rbtx4939_ioc_irq_mask(struct irq_data *d)
-{
- int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
-
- writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
- mmiowb();
-}
-
-static struct irq_chip rbtx4939_ioc_irq_chip = {
- .name = "IOC",
- .irq_mask = rbtx4939_ioc_irq_mask,
- .irq_unmask = rbtx4939_ioc_irq_unmask,
-};
-
-
-static inline int rbtx4939_ioc_irqroute(void)
-{
- unsigned char istat = readb(rbtx4939_ifac2_addr);
-
- if (unlikely(istat == 0))
- return -1;
- return RBTX4939_IRQ_IOC + __fls8(istat);
-}
-
-static int rbtx4939_irq_dispatch(int pending)
-{
- int irq;
-
- if (pending & CAUSEF_IP7)
- return MIPS_CPU_IRQ_BASE + 7;
- irq = tx4939_irq();
- if (likely(irq >= 0)) {
- /* redirect IOC interrupts */
- switch (irq) {
- case RBTX4939_IRQ_IOCINT:
- irq = rbtx4939_ioc_irqroute();
- break;
- }
- } else if (pending & CAUSEF_IP0)
- irq = MIPS_CPU_IRQ_BASE + 0;
- else if (pending & CAUSEF_IP1)
- irq = MIPS_CPU_IRQ_BASE + 1;
- else
- irq = -1;
- return irq;
-}
-
-void __init rbtx4939_irq_setup(void)
-{
- int i;
-
- /* mask all IOC interrupts */
- writeb(0, rbtx4939_ien_addr);
-
- /* clear SoftInt interrupts */
- writeb(0, rbtx4939_softint_addr);
-
- txx9_irq_dispatch = rbtx4939_irq_dispatch;
-
- tx4939_irq_init();
- for (i = RBTX4939_IRQ_IOC;
- i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
- irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
- handle_level_irq);
-
- irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
-}
diff --git a/arch/mips/txx9/rbtx4939/prom.c b/arch/mips/txx9/rbtx4939/prom.c
deleted file mode 100644
index ba25ba1bd2ec..000000000000
--- a/arch/mips/txx9/rbtx4939/prom.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * rbtx4939 specific prom routines
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/rbtx4939.h>
-
-void __init rbtx4939_prom_init(void)
-{
- unsigned long start, size;
- u64 win;
- int i;
-
- for (i = 0; i < 4; i++) {
- if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
- continue;
- win = ____raw_readq(&tx4939_ddrcptr->win[i]);
- start = (unsigned long)(win >> 48);
- size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
- memblock_add(start << 20, size << 20);
- }
- txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
-}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
deleted file mode 100644
index ef29a9c2ffd6..000000000000
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * Toshiba RBTX4939 setup routines.
- * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
- * and RBTX49xx patch from CELF patch archive.
- *
- * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/interrupt.h>
-#include <linux/smc91x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/map.h>
-#include <asm/reboot.h>
-#include <asm/txx9/generic.h>
-#include <asm/txx9/pci.h>
-#include <asm/txx9/rbtx4939.h>
-
-static void rbtx4939_machine_restart(char *command)
-{
- local_irq_disable();
- writeb(1, rbtx4939_reseten_addr);
- writeb(1, rbtx4939_softreset_addr);
- while (1)
- ;
-}
-
-static void __init rbtx4939_time_init(void)
-{
- tx4939_time_init(0);
-}
-
-#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X)
-#define HAVE_RBTX4939_IOSWAB
-#define IS_CE1_ADDR(addr) \
- ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
-static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
-{
- return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
-}
-static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
-{
- return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
-}
-#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
-
-static void __init rbtx4939_pci_setup(void)
-{
-#ifdef CONFIG_PCI
- int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
- struct pci_controller *c = &txx9_primary_pcic;
-
- register_pci_controller(c);
-
- tx4939_report_pciclk();
- tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
- if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
- (__raw_readq(&tx4939_ccfgptr->pcfg) &
- (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
- tx4939_report_pci1clk();
-
- /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
- c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
- register_pci_controller(c);
- tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
- }
-
- tx4939_setup_pcierr_irq();
-#endif /* CONFIG_PCI */
-}
-
-static unsigned long long default_ebccr[] __initdata = {
- 0x01c0000000007608ULL, /* 64M ROM */
- 0x017f000000007049ULL, /* 1M IOC */
- 0x0180000000408608ULL, /* ISA */
- 0,
-};
-
-static void __init rbtx4939_ebusc_setup(void)
-{
- int i;
- unsigned int sp;
-
- /* use user-configured speed */
- sp = TX4939_EBUSC_CR(0) & 0x30;
- default_ebccr[0] |= sp;
- default_ebccr[1] |= sp;
- default_ebccr[2] |= sp;
- /* initialise by myself */
- for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
- if (default_ebccr[i])
- ____raw_writeq(default_ebccr[i],
- &tx4939_ebuscptr->cr[i]);
- else
- ____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
- & ~8,
- &tx4939_ebuscptr->cr[i]);
- }
-}
-
-static void __init rbtx4939_update_ioc_pen(void)
-{
- __u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
- __u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
- __u8 pe1 = readb(rbtx4939_pe1_addr);
- __u8 pe2 = readb(rbtx4939_pe2_addr);
- __u8 pe3 = readb(rbtx4939_pe3_addr);
- if (pcfg & TX4939_PCFG_ATA0MODE)
- pe1 |= RBTX4939_PE1_ATA(0);
- else
- pe1 &= ~RBTX4939_PE1_ATA(0);
- if (pcfg & TX4939_PCFG_ATA1MODE) {
- pe1 |= RBTX4939_PE1_ATA(1);
- pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
- } else {
- pe1 &= ~RBTX4939_PE1_ATA(1);
- if (pcfg & TX4939_PCFG_ET0MODE)
- pe1 |= RBTX4939_PE1_RMII(0);
- else
- pe1 &= ~RBTX4939_PE1_RMII(0);
- if (pcfg & TX4939_PCFG_ET1MODE)
- pe1 |= RBTX4939_PE1_RMII(1);
- else
- pe1 &= ~RBTX4939_PE1_RMII(1);
- }
- if (ccfg & TX4939_CCFG_PTSEL)
- pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
- RBTX4939_PE3_VP_S);
- else {
- __u64 vmode = pcfg &
- (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
- if (vmode == 0)
- pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
- RBTX4939_PE3_VP_S);
- else if (vmode == TX4939_PCFG_VPSMODE) {
- pe3 |= RBTX4939_PE3_VP_P;
- pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
- } else if (vmode == TX4939_PCFG_VSSMODE) {
- pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
- pe3 &= ~RBTX4939_PE3_VP_P;
- } else {
- pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
- pe3 &= ~RBTX4939_PE3_VP_S;
- }
- }
- if (pcfg & TX4939_PCFG_SPIMODE) {
- if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
- pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
- else {
- if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
- pe2 |= RBTX4939_PE2_SIO2;
- pe2 &= ~RBTX4939_PE2_SIO0;
- } else {
- pe2 |= RBTX4939_PE2_SIO0;
- pe2 &= ~RBTX4939_PE2_SIO2;
- }
- }
- if (pcfg & TX4939_PCFG_SIO3MODE)
- pe2 |= RBTX4939_PE2_SIO3;
- else
- pe2 &= ~RBTX4939_PE2_SIO3;
- pe2 &= ~RBTX4939_PE2_SPI;
- } else {
- pe2 |= RBTX4939_PE2_SPI;
- pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
- RBTX4939_PE2_SIO0);
- }
- if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
- pe2 |= RBTX4939_PE2_GPIO;
- else
- pe2 &= ~RBTX4939_PE2_GPIO;
- writeb(pe1, rbtx4939_pe1_addr);
- writeb(pe2, rbtx4939_pe2_addr);
- writeb(pe3, rbtx4939_pe3_addr);
-}
-
-#define RBTX4939_MAX_7SEGLEDS 8
-
-#if IS_BUILTIN(CONFIG_LEDS_CLASS)
-static u8 led_val[RBTX4939_MAX_7SEGLEDS];
-struct rbtx4939_led_data {
- struct led_classdev cdev;
- char name[32];
- unsigned int num;
-};
-
-/* Use "dot" in 7seg LEDs */
-static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
- enum led_brightness value)
-{
- struct rbtx4939_led_data *led_dat =
- container_of(led_cdev, struct rbtx4939_led_data, cdev);
- unsigned int num = led_dat->num;
- unsigned long flags;
-
- local_irq_save(flags);
- led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
- writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
- local_irq_restore(flags);
-}
-
-static int __init rbtx4939_led_probe(struct platform_device *pdev)
-{
- struct rbtx4939_led_data *leds_data;
- int i;
- static char *default_triggers[] __initdata = {
- "heartbeat",
- "disk-activity",
- "nand-disk",
- };
-
- leds_data = kcalloc(RBTX4939_MAX_7SEGLEDS, sizeof(*leds_data),
- GFP_KERNEL);
- if (!leds_data)
- return -ENOMEM;
- for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
- int rc;
- struct rbtx4939_led_data *led_dat = &leds_data[i];
-
- led_dat->num = i;
- led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
- sprintf(led_dat->name, "rbtx4939:amber:%u", i);
- led_dat->cdev.name = led_dat->name;
- if (i < ARRAY_SIZE(default_triggers))
- led_dat->cdev.default_trigger = default_triggers[i];
- rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
- if (rc < 0)
- return rc;
- led_dat->cdev.brightness_set(&led_dat->cdev, 0);
- }
- return 0;
-
-}
-
-static struct platform_driver rbtx4939_led_driver = {
- .driver = {
- .name = "rbtx4939-led",
- },
-};
-
-static void __init rbtx4939_led_setup(void)
-{
- platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
- platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
-}
-#else
-static inline void rbtx4939_led_setup(void)
-{
-}
-#endif
-
-static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
-{
-#if IS_BUILTIN(CONFIG_LEDS_CLASS)
- unsigned long flags;
- local_irq_save(flags);
- /* bit7: reserved for LED class */
- led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
- val = led_val[pos];
- local_irq_restore(flags);
-#endif
- writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
-}
-
-static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
-{
- /* convert from map_to_seg7() notation */
- val = (val & 0x88) |
- ((val & 0x40) >> 6) |
- ((val & 0x20) >> 4) |
- ((val & 0x10) >> 2) |
- ((val & 0x04) << 2) |
- ((val & 0x02) << 4) |
- ((val & 0x01) << 6);
- __rbtx4939_7segled_putc(pos, val);
-}
-
-#if IS_ENABLED(CONFIG_MTD_RBTX4939)
-/* special mapping for boot rom */
-static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
-{
- u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
- unsigned char shift;
-
- if (bdipsw & 8) {
- /* BOOT Mode: USER ROM1 / USER ROM2 */
- shift = bdipsw & 3;
- /* rotate A[23:22] */
- return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22);
- }
-#ifdef __BIG_ENDIAN
- if (bdipsw == 0)
- /* BOOT Mode: Monitor ROM */
- ofs ^= 0x400000; /* swap A[22] */
-#endif
- return ofs;
-}
-
-static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs)
-{
- map_word r;
-
- ofs = rbtx4939_flash_fixup_ofs(ofs);
- r.x[0] = __raw_readw(map->virt + ofs);
- return r;
-}
-
-static void rbtx4939_flash_write16(struct map_info *map, const map_word datum,
- unsigned long ofs)
-{
- ofs = rbtx4939_flash_fixup_ofs(ofs);
- __raw_writew(datum.x[0], map->virt + ofs);
- mb(); /* see inline_map_write() in mtd/map.h */
-}
-
-static void rbtx4939_flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
- unsigned char shift;
- ssize_t curlen;
-
- from += (unsigned long)map->virt;
- if (bdipsw & 8) {
- /* BOOT Mode: USER ROM1 / USER ROM2 */
- shift = bdipsw & 3;
- while (len) {
- curlen = min_t(unsigned long, len,
- 0x400000 - (from & (0x400000 - 1)));
- memcpy(to,
- (void *)((from & ~0xc00000) |
- ((((from >> 22) + shift) & 3) << 22)),
- curlen);
- len -= curlen;
- from += curlen;
- to += curlen;
- }
- return;
- }
-#ifdef __BIG_ENDIAN
- if (bdipsw == 0) {
- /* BOOT Mode: Monitor ROM */
- while (len) {
- curlen = min_t(unsigned long, len,
- 0x400000 - (from & (0x400000 - 1)));
- memcpy(to, (void *)(from ^ 0x400000), curlen);
- len -= curlen;
- from += curlen;
- to += curlen;
- }
- return;
- }
-#endif
- memcpy(to, (void *)from, len);
-}
-
-static void rbtx4939_flash_map_init(struct map_info *map)
-{
- map->read = rbtx4939_flash_read16;
- map->write = rbtx4939_flash_write16;
- map->copy_from = rbtx4939_flash_copy_from;
-}
-
-static void __init rbtx4939_mtd_init(void)
-{
- static struct {
- struct platform_device dev;
- struct resource res;
- struct rbtx4939_flash_data data;
- } pdevs[4];
- int i;
- static char names[4][8];
- static struct mtd_partition parts[4];
- struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data;
- u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
-
- if (bdipsw & 8) {
- /* BOOT Mode: USER ROM1 / USER ROM2 */
- boot_pdata->nr_parts = 4;
- for (i = 0; i < boot_pdata->nr_parts; i++) {
- sprintf(names[i], "img%d", 4 - i);
- parts[i].name = names[i];
- parts[i].size = 0x400000;
- parts[i].offset = MTDPART_OFS_NXTBLK;
- }
- } else if (bdipsw == 0) {
- /* BOOT Mode: Monitor ROM */
- boot_pdata->nr_parts = 2;
- strcpy(names[0], "big");
- strcpy(names[1], "little");
- for (i = 0; i < boot_pdata->nr_parts; i++) {
- parts[i].name = names[i];
- parts[i].size = 0x400000;
- parts[i].offset = MTDPART_OFS_NXTBLK;
- }
- } else {
- /* BOOT Mode: ROM Emulator */
- boot_pdata->nr_parts = 2;
- parts[0].name = "boot";
- parts[0].offset = 0xc00000;
- parts[0].size = 0x400000;
- parts[1].name = "user";
- parts[1].offset = 0;
- parts[1].size = 0xc00000;
- }
- boot_pdata->parts = parts;
- boot_pdata->map_init = rbtx4939_flash_map_init;
-
- for (i = 0; i < ARRAY_SIZE(pdevs); i++) {
- struct resource *r = &pdevs[i].res;
- struct platform_device *dev = &pdevs[i].dev;
-
- r->start = 0x1f000000 - i * 0x1000000;
- r->end = r->start + 0x1000000 - 1;
- r->flags = IORESOURCE_MEM;
- pdevs[i].data.width = 2;
- dev->num_resources = 1;
- dev->resource = r;
- dev->id = i;
- dev->name = "rbtx4939-flash";
- dev->dev.platform_data = &pdevs[i].data;
- platform_device_register(dev);
- }
-}
-#else
-static void __init rbtx4939_mtd_init(void)
-{
-}
-#endif
-
-static void __init rbtx4939_arch_init(void)
-{
- rbtx4939_pci_setup();
-}
-
-static void __init rbtx4939_device_init(void)
-{
- unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
- struct resource smc_res[] = {
- {
- .start = smc_addr,
- .end = smc_addr + 0x10 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RBTX4939_IRQ_ETHER,
- /* override default irq flag defined in smc91x.h */
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
- },
- };
- struct smc91x_platdata smc_pdata = {
- .flags = SMC91X_USE_16BIT,
- };
- struct platform_device *pdev;
-#if IS_ENABLED(CONFIG_TC35815)
- int i, j;
- unsigned char ethaddr[2][6];
- u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
-
- for (i = 0; i < 2; i++) {
- unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
- if (bdipsw == 0)
- memcpy(ethaddr[i], (void *)area, 6);
- else {
- u16 buf[3];
- if (bdipsw & 8)
- area -= 0x03000000;
- else
- area -= 0x01000000;
- for (j = 0; j < 3; j++)
- buf[j] = le16_to_cpup((u16 *)(area + j * 2));
- memcpy(ethaddr[i], buf, 6);
- }
- }
- tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
-#endif
- pdev = platform_device_alloc("smc91x", -1);
- if (!pdev ||
- platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
- platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
- platform_device_add(pdev))
- platform_device_put(pdev);
- rbtx4939_mtd_init();
- /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
- tx4939_ndfmc_init(10, 35,
- (1 << 1) | (1 << 2),
- (1 << 2)); /* ch1:8bit, ch2:16bit */
- rbtx4939_led_setup();
- tx4939_wdt_init();
- tx4939_ata_init();
- tx4939_rtc_init();
- tx4939_dmac_init(0, 2);
- tx4939_aclc_init();
- platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
- tx4939_sramc_init();
- tx4939_rng_init();
-}
-
-static void __init rbtx4939_setup(void)
-{
- int i;
-
- rbtx4939_ebusc_setup();
- /* always enable ATA0 */
- txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
- if (txx9_master_clock == 0)
- txx9_master_clock = 20000000;
- tx4939_setup();
- rbtx4939_update_ioc_pen();
-#ifdef HAVE_RBTX4939_IOSWAB
- ioswabw = rbtx4939_ioswabw;
- __mem_ioswabw = rbtx4939_mem_ioswabw;
-#endif
-
- _machine_restart = rbtx4939_machine_restart;
-
- txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
- for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
- txx9_7segled_putc(i, '-');
- pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
- readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
- readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
-
-#ifdef CONFIG_PCI
- txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
- txx9_board_pcibios_setup = tx4927_pcibios_setup;
-#else
- set_io_port_base(RBTX4939_ETHER_BASE);
-#endif
-
- tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
-}
-
-struct txx9_board_vec rbtx4939_vec __initdata = {
- .system = "Toshiba RBTX4939",
- .prom_init = rbtx4939_prom_init,
- .mem_setup = rbtx4939_setup,
- .irq_setup = rbtx4939_irq_setup,
- .time_init = rbtx4939_time_init,
- .device_init = rbtx4939_device_init,
- .arch_init = rbtx4939_arch_init,
-#ifdef CONFIG_PCI
- .pci_map_irq = tx4939_pci_map_irq,
-#endif
-};
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 001b819f5298..9704963f9d50 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -226,19 +226,6 @@ config HW_RANDOM_VIRTIO
To compile this driver as a module, choose M here: the
module will be called virtio-rng. If unsure, say N.
-config HW_RANDOM_TX4939
- tristate "TX4939 Random Number Generator support"
- depends on SOC_TX4939
- default HW_RANDOM
- help
- This driver provides kernel-side support for the Random Number
- Generator hardware found on TX4939 SoC.
-
- To compile this driver as a module, choose M here: the
- module will be called tx4939-rng.
-
- If unsure, say Y.
-
config HW_RANDOM_MXC_RNGA
tristate "Freescale i.MX RNGA Random Number Generator"
depends on SOC_IMX31
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index a2f1ce0790d1..584d47ba32f7 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o
obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
-obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
obj-$(CONFIG_HW_RANDOM_IMX_RNGC) += imx-rngc.o
obj-$(CONFIG_HW_RANDOM_INGENIC_RNG) += ingenic-rng.o
diff --git a/drivers/char/hw_random/tx4939-rng.c b/drivers/char/hw_random/tx4939-rng.c
deleted file mode 100644
index c8bd34e740fd..000000000000
--- a/drivers/char/hw_random/tx4939-rng.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * RNG driver for TX4939 Random Number Generators (RNG)
- *
- * Copyright (C) 2009 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/hw_random.h>
-#include <linux/gfp.h>
-
-#define TX4939_RNG_RCSR 0x00000000
-#define TX4939_RNG_ROR(n) (0x00000018 + (n) * 8)
-
-#define TX4939_RNG_RCSR_INTE 0x00000008
-#define TX4939_RNG_RCSR_RST 0x00000004
-#define TX4939_RNG_RCSR_FIN 0x00000002
-#define TX4939_RNG_RCSR_ST 0x00000001
-
-struct tx4939_rng {
- struct hwrng rng;
- void __iomem *base;
- u64 databuf[3];
- unsigned int data_avail;
-};
-
-static void rng_io_start(void)
-{
-#ifndef CONFIG_64BIT
- /*
- * readq is reading a 64-bit register using a 64-bit load. On
- * a 32-bit kernel however interrupts or any other processor
- * exception would clobber the upper 32-bit of the processor
- * register so interrupts need to be disabled.
- */
- local_irq_disable();
-#endif
-}
-
-static void rng_io_end(void)
-{
-#ifndef CONFIG_64BIT
- local_irq_enable();
-#endif
-}
-
-static u64 read_rng(void __iomem *base, unsigned int offset)
-{
- return ____raw_readq(base + offset);
-}
-
-static void write_rng(u64 val, void __iomem *base, unsigned int offset)
-{
- return ____raw_writeq(val, base + offset);
-}
-
-static int tx4939_rng_data_present(struct hwrng *rng, int wait)
-{
- struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng);
- int i;
-
- if (rngdev->data_avail)
- return rngdev->data_avail;
- for (i = 0; i < 20; i++) {
- rng_io_start();
- if (!(read_rng(rngdev->base, TX4939_RNG_RCSR)
- & TX4939_RNG_RCSR_ST)) {
- rngdev->databuf[0] =
- read_rng(rngdev->base, TX4939_RNG_ROR(0));
- rngdev->databuf[1] =
- read_rng(rngdev->base, TX4939_RNG_ROR(1));
- rngdev->databuf[2] =
- read_rng(rngdev->base, TX4939_RNG_ROR(2));
- rngdev->data_avail =
- sizeof(rngdev->databuf) / sizeof(u32);
- /* Start RNG */
- write_rng(TX4939_RNG_RCSR_ST,
- rngdev->base, TX4939_RNG_RCSR);
- wait = 0;
- }
- rng_io_end();
- if (!wait)
- break;
- /* 90 bus clock cycles by default for generation */
- ndelay(90 * 5);
- }
- return rngdev->data_avail;
-}
-
-static int tx4939_rng_data_read(struct hwrng *rng, u32 *buffer)
-{
- struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng);
-
- rngdev->data_avail--;
- *buffer = *((u32 *)&rngdev->databuf + rngdev->data_avail);
- return sizeof(u32);
-}
-
-static int __init tx4939_rng_probe(struct platform_device *dev)
-{
- struct tx4939_rng *rngdev;
- int i;
-
- rngdev = devm_kzalloc(&dev->dev, sizeof(*rngdev), GFP_KERNEL);
- if (!rngdev)
- return -ENOMEM;
- rngdev->base = devm_platform_ioremap_resource(dev, 0);
- if (IS_ERR(rngdev->base))
- return PTR_ERR(rngdev->base);
-
- rngdev->rng.name = dev_name(&dev->dev);
- rngdev->rng.data_present = tx4939_rng_data_present;
- rngdev->rng.data_read = tx4939_rng_data_read;
-
- rng_io_start();
- /* Reset RNG */
- write_rng(TX4939_RNG_RCSR_RST, rngdev->base, TX4939_RNG_RCSR);
- write_rng(0, rngdev->base, TX4939_RNG_RCSR);
- /* Start RNG */
- write_rng(TX4939_RNG_RCSR_ST, rngdev->base, TX4939_RNG_RCSR);
- rng_io_end();
- /*
- * Drop first two results. From the datasheet:
- * The quality of the random numbers generated immediately
- * after reset can be insufficient. Therefore, do not use
- * random numbers obtained from the first and second
- * generations; use the ones from the third or subsequent
- * generation.
- */
- for (i = 0; i < 2; i++) {
- rngdev->data_avail = 0;
- if (!tx4939_rng_data_present(&rngdev->rng, 1))
- return -EIO;
- }
-
- platform_set_drvdata(dev, rngdev);
- return devm_hwrng_register(&dev->dev, &rngdev->rng);
-}
-
-static struct platform_driver tx4939_rng_driver = {
- .driver = {
- .name = "tx4939-rng",
- },
-};
-
-module_platform_driver_probe(tx4939_rng_driver, tx4939_rng_probe);
-
-MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver for TX4939");
-MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 4945caa88345..6a099bbcd8be 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -357,12 +357,6 @@ config MTD_INTEL_VR_NOR
Map driver for a NOR flash bank located on the Expansion Bus of the
Intel Vermilion Range chipset.
-config MTD_RBTX4939
- tristate "Map driver for RBTX4939 board"
- depends on TOSHIBA_RBTX4939 && MTD_CFI && MTD_COMPLEX_MAPPINGS
- help
- Map driver for NOR flash chips on RBTX4939 board.
-
config MTD_PLATRAM
tristate "Map driver for platform device RAM (mtd-ram)"
select MTD_RAM
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 11fea9c8d561..2240b100f66a 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -42,6 +42,5 @@ obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
-obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
obj-$(CONFIG_MTD_VMU) += vmu-flash.o
obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
diff --git a/drivers/mtd/maps/rbtx4939-flash.c b/drivers/mtd/maps/rbtx4939-flash.c
deleted file mode 100644
index 39c86c0b0ec1..000000000000
--- a/drivers/mtd/maps/rbtx4939-flash.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * rbtx4939-flash (based on physmap.c)
- *
- * This is a simplified physmap driver with map_init callback function.
- *
- * Copyright (C) 2009 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <asm/txx9/rbtx4939.h>
-
-struct rbtx4939_flash_info {
- struct mtd_info *mtd;
- struct map_info map;
-};
-
-static int rbtx4939_flash_remove(struct platform_device *dev)
-{
- struct rbtx4939_flash_info *info;
-
- info = platform_get_drvdata(dev);
- if (!info)
- return 0;
-
- if (info->mtd) {
- mtd_device_unregister(info->mtd);
- map_destroy(info->mtd);
- }
- return 0;
-}
-
-static const char * const rom_probe_types[] = {
- "cfi_probe", "jedec_probe", NULL };
-
-static int rbtx4939_flash_probe(struct platform_device *dev)
-{
- struct rbtx4939_flash_data *pdata;
- struct rbtx4939_flash_info *info;
- struct resource *res;
- const char * const *probe_type;
- int err = 0;
- unsigned long size;
-
- pdata = dev_get_platdata(&dev->dev);
- if (!pdata)
- return -ENODEV;
-
- res = platform_get_resource(dev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
- info = devm_kzalloc(&dev->dev, sizeof(struct rbtx4939_flash_info),
- GFP_KERNEL);
- if (!info)
- return -ENOMEM;
-
- platform_set_drvdata(dev, info);
-
- size = resource_size(res);
- pr_notice("rbtx4939 platform flash device: %pR\n", res);
-
- if (!devm_request_mem_region(&dev->dev, res->start, size,
- dev_name(&dev->dev)))
- return -EBUSY;
-
- info->map.name = dev_name(&dev->dev);
- info->map.phys = res->start;
- info->map.size = size;
- info->map.bankwidth = pdata->width;
-
- info->map.virt = devm_ioremap(&dev->dev, info->map.phys, size);
- if (!info->map.virt)
- return -EBUSY;
-
- if (pdata->map_init)
- (*pdata->map_init)(&info->map);
- else
- simple_map_init(&info->map);
-
- probe_type = rom_probe_types;
- for (; !info->mtd && *probe_type; probe_type++)
- info->mtd = do_map_probe(*probe_type, &info->map);
- if (!info->mtd) {
- dev_err(&dev->dev, "map_probe failed\n");
- err = -ENXIO;
- goto err_out;
- }
- info->mtd->dev.parent = &dev->dev;
- err = mtd_device_register(info->mtd, pdata->parts, pdata->nr_parts);
-
- if (err)
- goto err_out;
- return 0;
-
-err_out:
- rbtx4939_flash_remove(dev);
- return err;
-}
-
-#ifdef CONFIG_PM
-static void rbtx4939_flash_shutdown(struct platform_device *dev)
-{
- struct rbtx4939_flash_info *info = platform_get_drvdata(dev);
-
- if (mtd_suspend(info->mtd) == 0)
- mtd_resume(info->mtd);
-}
-#else
-#define rbtx4939_flash_shutdown NULL
-#endif
-
-static struct platform_driver rbtx4939_flash_driver = {
- .probe = rbtx4939_flash_probe,
- .remove = rbtx4939_flash_remove,
- .shutdown = rbtx4939_flash_shutdown,
- .driver = {
- .name = "rbtx4939-flash",
- },
-};
-
-module_platform_driver(rbtx4939_flash_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("RBTX4939 MTD map driver");
-MODULE_ALIAS("platform:rbtx4939-flash");
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 32b8738baa24..20408b7db540 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -309,7 +309,7 @@ config MTD_NAND_DAVINCI
config MTD_NAND_TXX9NDFMC
tristate "TXx9 NAND controller"
- depends on SOC_TX4938 || SOC_TX4939 || COMPILE_TEST
+ depends on SOC_TX4938 || COMPILE_TEST
depends on HAS_IOMEM
help
This enables the NAND flash controller on the TXx9 SoCs.
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 7fc5135ffbbf..aec8c9a3488b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -274,7 +274,7 @@ config PCIE_BRCMSTB
BMIPS_GENERIC || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
- default ARCH_BRCMSTB
+ default ARCH_BRCMSTB || BMIPS_GENERIC
help
Say Y here to enable PCIe host controller support for
Broadcom STB based SoCs, like the Raspberry Pi 4.
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 1fc7bd49a7ad..a267cd5b3233 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -118,6 +118,7 @@
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
#define PCIE_INTR2_CPU_BASE 0x4300
@@ -205,6 +206,8 @@ enum {
enum pcie_type {
GENERIC,
+ BCM7425,
+ BCM7435,
BCM4908,
BCM7278,
BCM2711,
@@ -223,6 +226,12 @@ static const int pcie_offsets[] = {
[EXT_CFG_DATA] = 0x9004,
};
+static const int pcie_offsets_bmips_7425[] = {
+ [RGR1_SW_INIT_1] = 0x8010,
+ [EXT_CFG_INDEX] = 0x8300,
+ [EXT_CFG_DATA] = 0x8304,
+};
+
static const struct pcie_cfg_data generic_cfg = {
.offsets = pcie_offsets,
.type = GENERIC,
@@ -230,6 +239,20 @@ static const struct pcie_cfg_data generic_cfg = {
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
};
+static const struct pcie_cfg_data bcm7425_cfg = {
+ .offsets = pcie_offsets_bmips_7425,
+ .type = BCM7425,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const struct pcie_cfg_data bcm7435_cfg = {
+ .offsets = pcie_offsets,
+ .type = BCM7435,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
static const struct pcie_cfg_data bcm4908_cfg = {
.offsets = pcie_offsets,
.type = BCM4908,
@@ -297,6 +320,11 @@ struct brcm_pcie {
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
};
+static inline bool is_bmips(const struct brcm_pcie *pcie)
+{
+ return pcie->type == BCM7435 || pcie->type == BCM7425;
+}
+
/*
* This is to convert the size of the inbound "BAR" region to the
* non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
@@ -443,6 +471,9 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
+ if (is_bmips(pcie))
+ return;
+
/* Write the cpu & limit addr upper bits */
high_addr_shift =
HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
@@ -718,12 +749,35 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
return base + PCIE_EXT_CFG_DATA + where;
}
+static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devfn,
+ int where)
+{
+ struct brcm_pcie *pcie = bus->sysdata;
+ void __iomem *base = pcie->base;
+ int idx;
+
+ /* Accesses to the RC go right to the RC registers if slot==0 */
+ if (pci_is_root_bus(bus))
+ return PCI_SLOT(devfn) ? NULL : base + (where & ~0x3);
+
+ /* For devices, write to the config space index register */
+ idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & ~3));
+ writel(idx, base + IDX_ADDR(pcie));
+ return base + DATA_ADDR(pcie);
+}
+
static struct pci_ops brcm_pcie_ops = {
.map_bus = brcm_pcie_map_conf,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
};
+static struct pci_ops brcm_pcie_ops32 = {
+ .map_bus = brcm_pcie_map_conf32,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
{
u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
@@ -883,7 +937,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
pcie->bridge_sw_init_set(pcie, 0);
tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
- tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
+ if (is_bmips(pcie))
+ tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
+ else
+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
/* Wait for SerDes to be stable */
usleep_range(100, 200);
@@ -893,8 +950,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
* is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
* is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
*/
- if (pcie->type == BCM2711)
- burst = 0x0; /* 128B */
+ if (is_bmips(pcie))
+ burst = 0x1; /* 256 bytes */
+ else if (pcie->type == BCM2711)
+ burst = 0x0; /* 128 bytes */
else if (pcie->type == BCM7278)
burst = 0x3; /* 512 bytes */
else
@@ -988,6 +1047,19 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
return -EINVAL;
}
+ if (is_bmips(pcie)) {
+ u64 start = res->start;
+ unsigned int j, nwins = resource_size(res) / SZ_128M;
+
+ /* bmips PCIe outbound windows have a 128MB max size */
+ if (nwins > BRCM_NUM_PCIE_OUT_WINS)
+ nwins = BRCM_NUM_PCIE_OUT_WINS;
+ for (j = 0; j < nwins; j++, start += SZ_128M)
+ brcm_pcie_set_outbound_win(pcie, j, start,
+ start - entry->offset,
+ SZ_128M);
+ break;
+ }
brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
res->start - entry->offset,
resource_size(res));
@@ -1226,6 +1298,8 @@ static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
+ { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
+ { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
{},
};
@@ -1315,7 +1389,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
}
}
- bridge->ops = &brcm_pcie_ops;
+ bridge->ops = pcie->type == BCM7425 ? &brcm_pcie_ops32 : &brcm_pcie_ops;
bridge->sysdata = pcie;
platform_set_drvdata(pdev, pcie);
diff --git a/drivers/platform/mips/Kconfig b/drivers/platform/mips/Kconfig
index 8ac149173c64..d421e1482395 100644
--- a/drivers/platform/mips/Kconfig
+++ b/drivers/platform/mips/Kconfig
@@ -30,4 +30,10 @@ config RS780E_ACPI
help
Loongson RS780E PCH ACPI Controller driver.
+config LS2K_RESET
+ bool "Loongson-2K1000 Reset Controller"
+ depends on MACH_LOONGSON64 || COMPILE_TEST
+ help
+ Loongson-2K1000 Reset Controller driver.
+
endif # MIPS_PLATFORM_DEVICES
diff --git a/drivers/platform/mips/Makefile b/drivers/platform/mips/Makefile
index 178149098777..4c71444e453a 100644
--- a/drivers/platform/mips/Makefile
+++ b/drivers/platform/mips/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CPU_HWMON) += cpu_hwmon.o
obj-$(CONFIG_RS780E_ACPI) += rs780e-acpi.o
+obj-$(CONFIG_LS2K_RESET) += ls2k-reset.o
diff --git a/drivers/platform/mips/ls2k-reset.c b/drivers/platform/mips/ls2k-reset.c
new file mode 100644
index 000000000000..8f42d5d16480
--- /dev/null
+++ b/drivers/platform/mips/ls2k-reset.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021, Qing Zhang <zhangqing@loongson.cn>
+ * Loongson-2K1000 reset support
+ */
+
+#include <linux/of_address.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+
+#define PM1_STS 0x0c /* Power Management 1 Status Register */
+#define PM1_CNT 0x14 /* Power Management 1 Control Register */
+#define RST_CNT 0x30 /* Reset Control Register */
+
+static void __iomem *base;
+
+static void ls2k_restart(char *command)
+{
+ writel(0x1, base + RST_CNT);
+}
+
+static void ls2k_poweroff(void)
+{
+ /* Clear */
+ writel((readl(base + PM1_STS) & 0xffffffff), base + PM1_STS);
+ /* Sleep Enable | Soft Off*/
+ writel(GENMASK(12, 10) | BIT(13), base + PM1_CNT);
+}
+
+static int ls2k_reset_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "loongson,ls2k-pm");
+ if (!np) {
+ pr_info("Failed to get PM node\n");
+ return -ENODEV;
+ }
+
+ base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!base) {
+ pr_info("Failed to map PM register base address\n");
+ return -ENOMEM;
+ }
+
+ _machine_restart = ls2k_restart;
+ pm_power_off = ls2k_poweroff;
+
+ return 0;
+}
+
+arch_initcall(ls2k_reset_init);