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amd64_edac: Correct erratum 505 range

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Basically we want to cover all 0x0-0xf models, i.e. Orochi and later.

Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/20130819192321.GF4165@pd.tnic
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Borislav Petkov 2013-08-24 11:25:00 +02:00
parent c874b6ba55
commit 3f0aba4fc0
1 changed files with 4 additions and 4 deletions
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8
drivers/edac/amd64_edac.c
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@ -206,8 +206,8 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
if (pvt->fam == 0xf)
min_scrubrate = 0x0;
/* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
/* Erratum #505 */
if (pvt->fam == 0x15 && pvt->model < 0x10)
f15h_select_dct(pvt, 0);
return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
@ -219,8 +219,8 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
u32 scrubval = 0;
int i, retval = -EINVAL;
/* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
/* Erratum #505 */
if (pvt->fam == 0x15 && pvt->model < 0x10)
f15h_select_dct(pvt, 0);
amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);