forked from Minki/linux
drm/bridge: tc358767: Simplify tc_set_video_mode()
Simplify tc_set_video_mode() by replacing explicit shifting using macros from <linux/bitfield.h>. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190619052716.16831-5-andrew.smirnov@gmail.com
This commit is contained in:
Andrey Smirnov
Andrzej Hajda
parent
aa92213f38
commit
3f072c304c
@ -15,6 +15,7 @@
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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@ -47,6 +48,7 @@
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/* Video Path */
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#define VPCTRL0 0x0450
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#define VSDELAY GENMASK(31, 20)
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#define OPXLFMT_RGB666 (0 << 8)
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#define OPXLFMT_RGB888 (1 << 8)
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#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
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@ -54,9 +56,17 @@
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#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
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#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
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#define HTIM01 0x0454
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#define HPW GENMASK(8, 0)
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#define HBPR GENMASK(24, 16)
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#define HTIM02 0x0458
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#define HDISPR GENMASK(10, 0)
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#define HFPR GENMASK(24, 16)
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#define VTIM01 0x045c
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#define VSPR GENMASK(7, 0)
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#define VBPR GENMASK(23, 16)
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#define VTIM02 0x0460
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#define VFPR GENMASK(23, 16)
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#define VDISPR GENMASK(10, 0)
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#define VFUEN0 0x0464
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#define VFUEN BIT(0) /* Video Frame Timing Upload */
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@ -99,14 +109,28 @@
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/* Main Channel */
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#define DP0_SECSAMPLE 0x0640
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#define DP0_VIDSYNCDELAY 0x0644
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#define VID_SYNC_DLY GENMASK(15, 0)
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#define THRESH_DLY GENMASK(31, 16)
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#define DP0_TOTALVAL 0x0648
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#define H_TOTAL GENMASK(15, 0)
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#define V_TOTAL GENMASK(31, 16)
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#define DP0_STARTVAL 0x064c
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#define H_START GENMASK(15, 0)
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#define V_START GENMASK(31, 16)
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#define DP0_ACTIVEVAL 0x0650
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#define H_ACT GENMASK(15, 0)
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#define V_ACT GENMASK(31, 16)
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#define DP0_SYNCVAL 0x0654
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#define VS_WIDTH GENMASK(30, 16)
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#define HS_WIDTH GENMASK(14, 0)
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#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
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#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
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#define DP0_MISC 0x0658
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#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
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#define MAX_TU_SYMBOL GENMASK(28, 23)
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#define TU_SIZE GENMASK(21, 16)
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#define BPC_6 (0 << 5)
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#define BPC_8 (1 << 5)
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@ -183,6 +207,12 @@
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/* Test & Debug */
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#define TSTCTL 0x0a00
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#define COLOR_R GENMASK(31, 24)
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#define COLOR_G GENMASK(23, 16)
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#define COLOR_B GENMASK(15, 8)
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#define ENI2CFILTER BIT(4)
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#define COLOR_BAR_MODE GENMASK(1, 0)
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#define COLOR_BAR_MODE_BARS 2
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#define PLL_DBG 0x0a04
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static bool tc_test_pattern;
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@ -663,6 +693,7 @@ static int tc_set_video_mode(struct tc_data *tc,
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int upper_margin = mode->vtotal - mode->vsync_end;
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int lower_margin = mode->vsync_start - mode->vdisplay;
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int vsync_len = mode->vsync_end - mode->vsync_start;
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u32 dp0_syncval;
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/*
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* Recommended maximum number of symbols transferred in a transfer unit:
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@ -687,50 +718,69 @@ static int tc_set_video_mode(struct tc_data *tc,
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* assume we do not need any delay when DPI is a source of
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* sync signals
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*/
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tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
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tc_write(VPCTRL0,
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FIELD_PREP(VSDELAY, 0) |
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OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
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tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
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(ALIGN(hsync_len, 2) << 0)); /* Hsync */
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tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
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(ALIGN(mode->hdisplay, 2) << 0)); /* width */
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tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
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(vsync_len << 0)); /* Vsync */
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tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
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(mode->vdisplay << 0)); /* height */
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tc_write(HTIM01,
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FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
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FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
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tc_write(HTIM02,
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FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
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FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
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tc_write(VTIM01,
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FIELD_PREP(VBPR, upper_margin) |
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FIELD_PREP(VSPR, vsync_len));
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tc_write(VTIM02,
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FIELD_PREP(VFPR, lower_margin) |
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FIELD_PREP(VDISPR, mode->vdisplay));
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tc_write(VFUEN0, VFUEN); /* update settings */
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/* Test pattern settings */
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tc_write(TSTCTL,
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(120 << 24) | /* Red Color component value */
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(20 << 16) | /* Green Color component value */
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(99 << 8) | /* Blue Color component value */
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(1 << 4) | /* Enable I2C Filter */
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(2 << 0) | /* Color bar Mode */
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0);
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FIELD_PREP(COLOR_R, 120) |
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FIELD_PREP(COLOR_G, 20) |
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FIELD_PREP(COLOR_B, 99) |
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ENI2CFILTER |
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FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
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/* DP Main Stream Attributes */
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vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
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tc_write(DP0_VIDSYNCDELAY,
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(max_tu_symbol << 16) | /* thresh_dly */
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(vid_sync_dly << 0));
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FIELD_PREP(THRESH_DLY, max_tu_symbol) |
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FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
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tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
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tc_write(DP0_TOTALVAL,
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FIELD_PREP(H_TOTAL, mode->htotal) |
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FIELD_PREP(V_TOTAL, mode->vtotal));
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tc_write(DP0_STARTVAL,
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((upper_margin + vsync_len) << 16) |
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((left_margin + hsync_len) << 0));
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FIELD_PREP(H_START, left_margin + hsync_len) |
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FIELD_PREP(V_START, upper_margin + vsync_len));
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tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
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tc_write(DP0_ACTIVEVAL,
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FIELD_PREP(V_ACT, mode->vdisplay) |
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FIELD_PREP(H_ACT, mode->hdisplay));
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tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
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((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
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((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
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dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
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FIELD_PREP(HS_WIDTH, hsync_len);
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tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
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DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
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tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
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BPC_8);
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
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tc_write(DP0_SYNCVAL, dp0_syncval);
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tc_write(DPIPXLFMT,
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VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
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DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
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DPI_BPP_RGB888);
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tc_write(DP0_MISC,
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FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
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FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
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BPC_8);
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return 0;
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err:
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