parisc architecture late bug fixes for kernel v5.16

- Fix a bug in the C code which calculates the relevant futex spinlock based on
   the futex virtual address. In some cases a wrong spinlock (compared to what
   is calculated in the assembly code path) was choosen which then can lead to
   deadlocks.
 
 - The 64-bit kernel missed to clip the LWS number in the Light-weight-syscall
   path for 32-bit processes.
 
 - Prevent CPU register dump to show stale value in IIR register on access rights traps.
 
 - Remove unused ARCH_DEFCONFIG entries.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYcNELQAKCRD3ErUQojoP
 X+pLAP9Ufu4MYYdEzm7uMTPgaeg0HryHS5zVR9w9iLboK2HzkgD/S1I15E61smx0
 Az/mhwr/uFtPd5tzAU1qUP7HMFk0wgg=
 =YhZ8
 -----END PGP SIGNATURE-----

Merge tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc architecture fixes from Helge Deller:

 - Fix a bug in the C code which calculates the relevant futex spinlock
   based on the futex virtual address. In some cases a wrong spinlock
   (compared to what is calculated in the assembly code path) was
   choosen which then can lead to deadlocks.

 - The 64-bit kernel missed to clip the LWS number in the
   Light-weight-syscall path for 32-bit processes.

 - Prevent CPU register dump to show stale value in IIR register on
   access rights traps.

 - Remove unused ARCH_DEFCONFIG entries.

* tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: remove ARCH_DEFCONFIG
  parisc: Fix mask used to select futex spinlock
  parisc: Correct completer in lws start
  parisc: Clear stale IIR value on instruction access rights trap
This commit is contained in:
Linus Torvalds 2021-12-22 10:17:16 -08:00
commit 3f066e882b
4 changed files with 5 additions and 8 deletions

View File

@ -85,11 +85,6 @@ config MMU
config STACK_GROWSUP
def_bool y
config ARCH_DEFCONFIG
string
default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT
default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT
config GENERIC_LOCKBREAK
bool
default y

View File

@ -14,7 +14,7 @@ static inline void
_futex_spin_lock(u32 __user *uaddr)
{
extern u32 lws_lock_start[];
long index = ((long)uaddr & 0x3f8) >> 1;
long index = ((long)uaddr & 0x7f8) >> 1;
arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
preempt_disable();
arch_spin_lock(s);
@ -24,7 +24,7 @@ static inline void
_futex_spin_unlock(u32 __user *uaddr)
{
extern u32 lws_lock_start[];
long index = ((long)uaddr & 0x3f8) >> 1;
long index = ((long)uaddr & 0x7f8) >> 1;
arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
arch_spin_unlock(s);
preempt_enable();

View File

@ -472,7 +472,7 @@ lws_start:
extrd,u %r1,PSW_W_BIT,1,%r1
/* sp must be aligned on 4, so deposit the W bit setting into
* the bottom of sp temporarily */
or,ev %r1,%r30,%r30
or,od %r1,%r30,%r30
/* Clip LWS number to a 32-bit value for 32-bit processes */
depdi 0, 31, 32, %r20

View File

@ -730,6 +730,8 @@ void notrace handle_interruption(int code, struct pt_regs *regs)
}
mmap_read_unlock(current->mm);
}
/* CPU could not fetch instruction, so clear stale IIR value. */
regs->iir = 0xbaadf00d;
fallthrough;
case 27:
/* Data memory protection ID trap */