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dt-bindings: Changes for v5.11-rc1

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This contains a couple of conversions of bindings to json-schema, as
 well as symbolic names for the various memory clients on Tegra20,
 Tegra30 and Tegra124. There's also a couple of fixes for Tegra194
 pinmux and ARM GIC bindings. Finally, a new vendor prefix is added
 for Ouya and the Ouya game console compatible string is defined.
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Merge tag 'tegra-for-5.11-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.11-rc1

This contains a couple of conversions of bindings to json-schema, as
well as symbolic names for the various memory clients on Tegra20,
Tegra30 and Tegra124. There's also a couple of fixes for Tegra194
pinmux and ARM GIC bindings. Finally, a new vendor prefix is added
for Ouya and the Ouya game console compatible string is defined.

* tag 'tegra-for-5.11-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: bus: Convert ACONNECT doc to json-schema
  dt-bindings: interrupt-controller: arm,gic: Update Tegra compatibles
  dt-bindings: dma: Convert ADMA doc to json-schema
  dt-bindings: Fix entry name for I/O High Voltage property
  dt-bindings: ARM: tegra: Add Ouya game console
  dt-bindings: Add vendor prefix for Ouya Inc.
  dt-bindings: memory: tegra124: Add memory client IDs
  dt-bindings: memory: tegra30: Add memory client IDs
  dt-bindings: memory: tegra20: Add memory client IDs

Link: https://lore.kernel.org/r/20201127144329.124891-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-11-27 18:03:16 +01:00
commit 3f02c6a828
11 changed files with 383 additions and 102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -71,6 +71,9 @@ properties:
- const: asus,tilapia
- const: asus,grouper
- const: nvidia,tegra30
- items:
- const: ouya,ouya
- const: nvidia,tegra30
- items:
- enum:
- nvidia,dalmore

44
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
View File

@ -1,44 +0,0 @@
NVIDIA Tegra ACONNECT Bus
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
Required properties:
- compatible: Must be "nvidia,tegra210-aconnect".
- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
and APE interface clock (TEGRA210_CLK_APB2APE).
- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
'clocks' entries.
- power-domains: Must contain a phandle that points to the audio powergate
(namely 'aud') for Tegra210.
- #address-cells: The number of cells used to represent physical base addresses
in the aconnect address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
range in the aconnect address space. Should be 1.
- ranges: Mapping of the aconnect address space to the CPU address space.
All devices accessed via the ACONNNECT are described by child-nodes.
Example:
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
child1 {
...
};
child2 {
...
};
};

82
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml Normal file
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@ -0,0 +1,82 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra ACONNECT Bus
description: |
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
devices accessed via the ACONNNECT are described by child-nodes.
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- const: nvidia,tegra210-aconnect
- items:
- enum:
- nvidia,tegra186-aconnect
- nvidia,tegra194-aconnect
- const: nvidia,tegra210-aconnect
clocks:
items:
- description: Must contain the entry for APE clock
- description: Must contain the entry for APE interface clock
clock-names:
items:
- const: ape
- const: apb2ape
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"@[0-9a-f]+$":
type: object
required:
- compatible
- clocks
- clock-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include<dt-bindings/clock/tegra210-car.h>
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x702c0000 0x00040000>;
// Child device nodes follow ...
};
...

56
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt
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@ -1,56 +0,0 @@
* NVIDIA Tegra Audio DMA (ADMA) controller
The Tegra Audio DMA controller that is used for transferring data
between system memory and the Audio Processing Engine (APE).
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra210-adma": for Tegra210
- "nvidia,tegra186-adma": for Tegra186 and Tegra194
- reg: Should contain DMA registers location and length. This should be
a single entry that includes all of the per-channel registers in one
contiguous bank.
- interrupts: Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
- clocks: Must contain one entry for the ADMA module clock
(TEGRA210_CLK_D_AUDIO).
- clock-names: Must contain the name "d_audio" for the corresponding
'clocks' entry.
- #dma-cells : Must be 1. The first cell denotes the receive/transmit
request number and should be between 1 and the maximum number of
requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
fields in the ADMA_CHn_CTRL register.
Example:
adma: dma@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x0 0x702e2000 0x0 0x2000>;
interrupt-parent = <&tegra_agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
#dma-cells = <1>;
};

99
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml Normal file
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@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Audio DMA (ADMA) controller
description: |
The Tegra Audio DMA controller is used for transferring data
between system memory and the Audio Processing Engine (APE).
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
allOf:
- $ref: "dma-controller.yaml#"
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra210-adma
- nvidia,tegra186-adma
- items:
- const: nvidia,tegra194-adma
- const: nvidia,tegra186-adma
reg:
maxItems: 1
interrupts:
description: |
Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
minItems: 1
maxItems: 32
clocks:
description: Must contain one entry for the ADMA module clock
maxItems: 1
clock-names:
const: d_audio
"#dma-cells":
description: |
The first cell denotes the receive/transmit request number and
should be between 1 and the maximum number of requests supported.
This value corresponds to the RX/TX_REQUEST_SELECT fields in the
ADMA_CHn_CTRL register.
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include<dt-bindings/clock/tegra210-car.h>
dma-controller@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x702e2000 0x2000>;
interrupt-parent = <&tegra_agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
#dma-cells = <1>;
};
...

9
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
View File

@ -35,7 +35,6 @@ properties:
- arm,gic-400
- arm,pl390
- arm,tc11mp-gic
- nvidia,tegra210-agic
- qcom,msm-8660-qgic
- qcom,msm-qgic2
@ -53,6 +52,14 @@ properties:
- const: brcm,brahma-b15-gic
- const: arm,cortex-a15-gic
- oneOf:
- const: nvidia,tegra210-agic
- items:
- enum:
- nvidia,tegra186-agic
- nvidia,tegra194-agic
- const: nvidia,tegra210-agic
interrupt-controller: true
"#address-cells":

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
View File

@ -99,7 +99,7 @@ Example:
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -794,6 +794,8 @@ patternProperties:
description: Ortus Technology Co., Ltd.
"^osddisplays,.*":
description: OSD Displays
"^ouya,.*":
description: Ouya Inc.
"^overkiz,.*":
description: Overkiz SAS
"^ovti,.*":

68
include/dt-bindings/memory/tegra124-mc.h
View File

@ -54,4 +54,72 @@
#define TEGRA124_MC_RESET_ISP2B 22
#define TEGRA124_MC_RESET_GPU 23
#define TEGRA124_MC_PTCR 0
#define TEGRA124_MC_DISPLAY0A 1
#define TEGRA124_MC_DISPLAY0AB 2
#define TEGRA124_MC_DISPLAY0B 3
#define TEGRA124_MC_DISPLAY0BB 4
#define TEGRA124_MC_DISPLAY0C 5
#define TEGRA124_MC_DISPLAY0CB 6
#define TEGRA124_MC_AFIR 14
#define TEGRA124_MC_AVPCARM7R 15
#define TEGRA124_MC_DISPLAYHC 16
#define TEGRA124_MC_DISPLAYHCB 17
#define TEGRA124_MC_HDAR 21
#define TEGRA124_MC_HOST1XDMAR 22
#define TEGRA124_MC_HOST1XR 23
#define TEGRA124_MC_MSENCSRD 28
#define TEGRA124_MC_PPCSAHBDMAR 29
#define TEGRA124_MC_PPCSAHBSLVR 30
#define TEGRA124_MC_SATAR 31
#define TEGRA124_MC_VDEBSEVR 34
#define TEGRA124_MC_VDEMBER 35
#define TEGRA124_MC_VDEMCER 36
#define TEGRA124_MC_VDETPER 37
#define TEGRA124_MC_MPCORELPR 38
#define TEGRA124_MC_MPCORER 39
#define TEGRA124_MC_MSENCSWR 43
#define TEGRA124_MC_AFIW 49
#define TEGRA124_MC_AVPCARM7W 50
#define TEGRA124_MC_HDAW 53
#define TEGRA124_MC_HOST1XW 54
#define TEGRA124_MC_MPCORELPW 56
#define TEGRA124_MC_MPCOREW 57
#define TEGRA124_MC_PPCSAHBDMAW 59
#define TEGRA124_MC_PPCSAHBSLVW 60
#define TEGRA124_MC_SATAW 61
#define TEGRA124_MC_VDEBSEVW 62
#define TEGRA124_MC_VDEDBGW 63
#define TEGRA124_MC_VDEMBEW 64
#define TEGRA124_MC_VDETPMW 65
#define TEGRA124_MC_ISPRA 68
#define TEGRA124_MC_ISPWA 70
#define TEGRA124_MC_ISPWB 71
#define TEGRA124_MC_XUSB_HOSTR 74
#define TEGRA124_MC_XUSB_HOSTW 75
#define TEGRA124_MC_XUSB_DEVR 76
#define TEGRA124_MC_XUSB_DEVW 77
#define TEGRA124_MC_ISPRAB 78
#define TEGRA124_MC_ISPWAB 80
#define TEGRA124_MC_ISPWBB 81
#define TEGRA124_MC_TSECSRD 84
#define TEGRA124_MC_TSECSWR 85
#define TEGRA124_MC_A9AVPSCR 86
#define TEGRA124_MC_A9AVPSCW 87
#define TEGRA124_MC_GPUSRD 88
#define TEGRA124_MC_GPUSWR 89
#define TEGRA124_MC_DISPLAYT 90
#define TEGRA124_MC_SDMMCRA 96
#define TEGRA124_MC_SDMMCRAA 97
#define TEGRA124_MC_SDMMCR 98
#define TEGRA124_MC_SDMMCRAB 99
#define TEGRA124_MC_SDMMCWA 100
#define TEGRA124_MC_SDMMCWAA 101
#define TEGRA124_MC_SDMMCW 102
#define TEGRA124_MC_SDMMCWAB 103
#define TEGRA124_MC_VICSRD 108
#define TEGRA124_MC_VICSWR 109
#define TEGRA124_MC_VIW 114
#define TEGRA124_MC_DISPLAYD 115
#endif

53
include/dt-bindings/memory/tegra20-mc.h
View File

@ -18,4 +18,57 @@
#define TEGRA20_MC_RESET_VDE 13
#define TEGRA20_MC_RESET_VI 14
#define TEGRA20_MC_DISPLAY0A 0
#define TEGRA20_MC_DISPLAY0AB 1
#define TEGRA20_MC_DISPLAY0B 2
#define TEGRA20_MC_DISPLAY0BB 3
#define TEGRA20_MC_DISPLAY0C 4
#define TEGRA20_MC_DISPLAY0CB 5
#define TEGRA20_MC_DISPLAY1B 6
#define TEGRA20_MC_DISPLAY1BB 7
#define TEGRA20_MC_EPPUP 8
#define TEGRA20_MC_G2PR 9
#define TEGRA20_MC_G2SR 10
#define TEGRA20_MC_MPEUNIFBR 11
#define TEGRA20_MC_VIRUV 12
#define TEGRA20_MC_AVPCARM7R 13
#define TEGRA20_MC_DISPLAYHC 14
#define TEGRA20_MC_DISPLAYHCB 15
#define TEGRA20_MC_FDCDRD 16
#define TEGRA20_MC_G2DR 17
#define TEGRA20_MC_HOST1XDMAR 18
#define TEGRA20_MC_HOST1XR 19
#define TEGRA20_MC_IDXSRD 20
#define TEGRA20_MC_MPCORER 21
#define TEGRA20_MC_MPE_IPRED 22
#define TEGRA20_MC_MPEAMEMRD 23
#define TEGRA20_MC_MPECSRD 24
#define TEGRA20_MC_PPCSAHBDMAR 25
#define TEGRA20_MC_PPCSAHBSLVR 26
#define TEGRA20_MC_TEXSRD 27
#define TEGRA20_MC_VDEBSEVR 28
#define TEGRA20_MC_VDEMBER 29
#define TEGRA20_MC_VDEMCER 30
#define TEGRA20_MC_VDETPER 31
#define TEGRA20_MC_EPPU 32
#define TEGRA20_MC_EPPV 33
#define TEGRA20_MC_EPPY 34
#define TEGRA20_MC_MPEUNIFBW 35
#define TEGRA20_MC_VIWSB 36
#define TEGRA20_MC_VIWU 37
#define TEGRA20_MC_VIWV 38
#define TEGRA20_MC_VIWY 39
#define TEGRA20_MC_G2DW 40
#define TEGRA20_MC_AVPCARM7W 41
#define TEGRA20_MC_FDCDWR 42
#define TEGRA20_MC_HOST1XW 43
#define TEGRA20_MC_ISPW 44
#define TEGRA20_MC_MPCOREW 45
#define TEGRA20_MC_MPECSWR 46
#define TEGRA20_MC_PPCSAHBDMAW 47
#define TEGRA20_MC_PPCSAHBSLVW 48
#define TEGRA20_MC_VDEBSEVW 49
#define TEGRA20_MC_VDEMBEW 50
#define TEGRA20_MC_VDETPMW 51
#endif

67
include/dt-bindings/memory/tegra30-mc.h
View File

@ -41,4 +41,71 @@
#define TEGRA30_MC_RESET_VDE 16
#define TEGRA30_MC_RESET_VI 17
#define TEGRA30_MC_PTCR 0
#define TEGRA30_MC_DISPLAY0A 1
#define TEGRA30_MC_DISPLAY0AB 2
#define TEGRA30_MC_DISPLAY0B 3
#define TEGRA30_MC_DISPLAY0BB 4
#define TEGRA30_MC_DISPLAY0C 5
#define TEGRA30_MC_DISPLAY0CB 6
#define TEGRA30_MC_DISPLAY1B 7
#define TEGRA30_MC_DISPLAY1BB 8
#define TEGRA30_MC_EPPUP 9
#define TEGRA30_MC_G2PR 10
#define TEGRA30_MC_G2SR 11
#define TEGRA30_MC_MPEUNIFBR 12
#define TEGRA30_MC_VIRUV 13
#define TEGRA30_MC_AFIR 14
#define TEGRA30_MC_AVPCARM7R 15
#define TEGRA30_MC_DISPLAYHC 16
#define TEGRA30_MC_DISPLAYHCB 17
#define TEGRA30_MC_FDCDRD 18
#define TEGRA30_MC_FDCDRD2 19
#define TEGRA30_MC_G2DR 20
#define TEGRA30_MC_HDAR 21
#define TEGRA30_MC_HOST1XDMAR 22
#define TEGRA30_MC_HOST1XR 23
#define TEGRA30_MC_IDXSRD 24
#define TEGRA30_MC_IDXSRD2 25
#define TEGRA30_MC_MPE_IPRED 26
#define TEGRA30_MC_MPEAMEMRD 27
#define TEGRA30_MC_MPECSRD 28
#define TEGRA30_MC_PPCSAHBDMAR 29
#define TEGRA30_MC_PPCSAHBSLVR 30
#define TEGRA30_MC_SATAR 31
#define TEGRA30_MC_TEXSRD 32
#define TEGRA30_MC_TEXSRD2 33
#define TEGRA30_MC_VDEBSEVR 34
#define TEGRA30_MC_VDEMBER 35
#define TEGRA30_MC_VDEMCER 36
#define TEGRA30_MC_VDETPER 37
#define TEGRA30_MC_MPCORELPR 38
#define TEGRA30_MC_MPCORER 39
#define TEGRA30_MC_EPPU 40
#define TEGRA30_MC_EPPV 41
#define TEGRA30_MC_EPPY 42
#define TEGRA30_MC_MPEUNIFBW 43
#define TEGRA30_MC_VIWSB 44
#define TEGRA30_MC_VIWU 45
#define TEGRA30_MC_VIWV 46
#define TEGRA30_MC_VIWY 47
#define TEGRA30_MC_G2DW 48
#define TEGRA30_MC_AFIW 49
#define TEGRA30_MC_AVPCARM7W 50
#define TEGRA30_MC_FDCDWR 51
#define TEGRA30_MC_FDCDWR2 52
#define TEGRA30_MC_HDAW 53
#define TEGRA30_MC_HOST1XW 54
#define TEGRA30_MC_ISPW 55
#define TEGRA30_MC_MPCORELPW 56
#define TEGRA30_MC_MPCOREW 57
#define TEGRA30_MC_MPECSWR 58
#define TEGRA30_MC_PPCSAHBDMAW 59
#define TEGRA30_MC_PPCSAHBSLVW 60
#define TEGRA30_MC_SATAW 61
#define TEGRA30_MC_VDEBSEVW 62
#define TEGRA30_MC_VDEDBGW 63
#define TEGRA30_MC_VDEMBEW 64
#define TEGRA30_MC_VDETPMW 65
#endif