forked from Minki/linux
clk: at91: rework PLL rate calculation
The AT91 PLL rate configuration is done by configuring a multiplier/divider pair. The previous calculation was over-complicated (and apparently buggy). Simplify the implementation and add some comments to explain what is done here. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: Gaël PORTAY <gael.portay@gmail.com> Tested-by: Gaël PORTAY <gael.portay@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Boris BREZILLON
Mike Turquette
parent
078a3eb519
commit
3ef9dd2bab
@ -15,6 +15,7 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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@ -29,6 +30,9 @@
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#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
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#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
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(layout)->mul_mask)
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#define PLL_MUL_MIN 2
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#define PLL_MUL_MASK(layout) ((layout)->mul_mask)
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#define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
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#define PLL_ICPR_SHIFT(id) ((id) * 16)
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#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
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#define PLL_MAX_COUNT 0x3f
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@ -163,99 +167,102 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
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unsigned long parent_rate,
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u32 *div, u32 *mul,
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u32 *index) {
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unsigned long maxrate;
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unsigned long minrate;
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unsigned long divrate;
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unsigned long bestdiv = 1;
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unsigned long bestmul;
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unsigned long tmpdiv;
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unsigned long roundup;
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unsigned long rounddown;
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unsigned long remainder;
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unsigned long bestremainder;
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unsigned long maxmul;
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unsigned long maxdiv;
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unsigned long mindiv;
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int i = 0;
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const struct clk_pll_layout *layout = pll->layout;
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const struct clk_pll_characteristics *characteristics =
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pll->characteristics;
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unsigned long bestremainder = ULONG_MAX;
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unsigned long maxdiv, mindiv, tmpdiv;
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long bestrate = -ERANGE;
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unsigned long bestdiv;
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unsigned long bestmul;
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int i = 0;
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/* Minimum divider = 1 */
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/* Maximum multiplier = max_mul */
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maxmul = layout->mul_mask + 1;
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maxrate = (parent_rate * maxmul) / 1;
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/* Maximum divider = max_div */
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/* Minimum multiplier = 2 */
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maxdiv = PLL_DIV_MAX;
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minrate = (parent_rate * 2) / maxdiv;
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/* Check if parent_rate is a valid input rate */
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if (parent_rate < characteristics->input.min ||
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parent_rate < characteristics->input.max)
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parent_rate > characteristics->input.max)
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return -ERANGE;
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if (parent_rate < minrate || parent_rate > maxrate)
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return -ERANGE;
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/*
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* Calculate minimum divider based on the minimum multiplier, the
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* parent_rate and the requested rate.
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* Should always be 2 according to the input and output characteristics
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* of the PLL blocks.
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*/
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mindiv = (parent_rate * PLL_MUL_MIN) / rate;
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if (!mindiv)
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mindiv = 1;
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/*
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* Calculate the maximum divider which is limited by PLL register
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* layout (limited by the MUL or DIV field size).
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*/
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maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
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if (maxdiv > PLL_DIV_MAX)
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maxdiv = PLL_DIV_MAX;
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/*
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* Iterate over the acceptable divider values to find the best
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* divider/multiplier pair (the one that generates the closest
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* rate to the requested one).
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*/
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for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
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unsigned long remainder;
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unsigned long tmprate;
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unsigned long tmpmul;
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/*
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* Calculate the multiplier associated with the current
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* divider that provide the closest rate to the requested one.
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*/
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tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
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tmprate = (parent_rate / tmpdiv) * tmpmul;
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if (tmprate > rate)
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remainder = tmprate - rate;
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else
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remainder = rate - tmprate;
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/*
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* Compare the remainder with the best remainder found until
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* now and elect a new best multiplier/divider pair if the
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* current remainder is smaller than the best one.
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*/
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if (remainder < bestremainder) {
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bestremainder = remainder;
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bestdiv = tmpdiv;
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bestmul = tmpmul;
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bestrate = tmprate;
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}
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/*
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* We've found a perfect match!
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* Stop searching now and use this multiplier/divider pair.
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*/
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if (!remainder)
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break;
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}
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/* We haven't found any multiplier/divider pair => return -ERANGE */
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if (bestrate < 0)
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return bestrate;
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/* Check if bestrate is a valid output rate */
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for (i = 0; i < characteristics->num_output; i++) {
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if (parent_rate >= characteristics->output[i].min &&
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parent_rate <= characteristics->output[i].max)
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if (bestrate >= characteristics->output[i].min &&
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bestrate <= characteristics->output[i].max)
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break;
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}
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if (i >= characteristics->num_output)
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return -ERANGE;
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bestmul = rate / parent_rate;
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rounddown = parent_rate % rate;
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roundup = rate - rounddown;
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bestremainder = roundup < rounddown ? roundup : rounddown;
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if (!bestremainder) {
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if (div)
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*div = bestdiv;
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if (mul)
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*mul = bestmul;
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if (index)
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*index = i;
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return rate;
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}
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maxdiv = 255 / (bestmul + 1);
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if (parent_rate / maxdiv < characteristics->input.min)
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maxdiv = parent_rate / characteristics->input.min;
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mindiv = parent_rate / characteristics->input.max;
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if (parent_rate % characteristics->input.max)
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mindiv++;
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for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
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divrate = parent_rate / tmpdiv;
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rounddown = rate % divrate;
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roundup = divrate - rounddown;
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remainder = roundup < rounddown ? roundup : rounddown;
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if (remainder < bestremainder) {
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bestremainder = remainder;
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bestmul = rate / divrate;
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bestdiv = tmpdiv;
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}
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if (!remainder)
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break;
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}
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rate = (parent_rate / bestdiv) * bestmul;
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if (div)
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*div = bestdiv;
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if (mul)
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*mul = bestmul;
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*mul = bestmul - 1;
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if (index)
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*index = i;
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return rate;
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return bestrate;
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}
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static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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