forked from Minki/linux
spi: bcm2835: enable dma modes for transfers meeting certain conditions
Conditions per spi_transfer are:
* transfer.len >= 96 bytes (to avoid mapping overhead costs)
* transfer.len < 65536 bytes (limitaion by spi-hw block - could get extended)
* an individual scatter/gather transfer length must be a multiple of 4
for anything but the last transfer - spi-hw block limit.
(some shortcut has been taken in can_dma to avoid unnecessary mapping of
pages which, for which there is a chance that there is a split with a
transfer length not a multiple of 4)
If it becomes a necessity these restrictions can get removed by additional
code.
Note that this patch requires a patch to dma-bcm2835.c by Noralf to
enable scatter-gather mode inside the dmaengine, which has not been
merged yet.
That is why no patch to arch/arm/boot/dts/bcm2835.dtsi is included - the
code works as before without dma when tx/rx are not set, but it writes
a message warning about dma not used:
spi-bcm2835 20204000.spi: no tx-dma configuration found - not using dma mode
To enable dma-mode add the following lines to the device-tree:
dmas = <&dma 6>, <&dma 7>;
dma-names = "tx", "rx";
Tested-by: Noralf Trønnes <noralf@tronnes.org> (private communication)
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Martin Sperl
Mark Brown
parent
e0d58cdcae
commit
3ecd37edaa
@ -23,15 +23,18 @@
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/spi/spi.h>
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/* SPI register offsets */
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@ -70,6 +73,7 @@
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#define BCM2835_SPI_POLLING_LIMIT_US 30
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#define BCM2835_SPI_POLLING_JIFFIES 2
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#define BCM2835_SPI_DMA_MIN_LENGTH 96
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_NO_CS | SPI_3WIRE)
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@ -83,6 +87,7 @@ struct bcm2835_spi {
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u8 *rx_buf;
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int tx_len;
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int rx_len;
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bool dma_pending;
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};
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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@ -128,12 +133,15 @@ static void bcm2835_spi_reset_hw(struct spi_master *master)
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/* Disable SPI interrupts and transfer */
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cs &= ~(BCM2835_SPI_CS_INTR |
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BCM2835_SPI_CS_INTD |
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BCM2835_SPI_CS_DMAEN |
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BCM2835_SPI_CS_TA);
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/* and reset RX/TX FIFOS */
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cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
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/* and reset the SPI_HW */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/* as well as DLEN */
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bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
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}
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static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
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@ -193,6 +201,279 @@ static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
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return 1;
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}
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/*
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* DMA support
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*
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* this implementation has currently a few issues in so far as it does
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* not work arrount limitations of the HW.
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*
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* the main one being that DMA transfers are limited to 16 bit
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* (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN
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*
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* also we currently assume that the scatter-gather fragments are
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* all multiple of 4 (except the last) - otherwise we would need
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* to reset the FIFO before subsequent transfers...
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* this also means that tx/rx transfers sg's need to be of equal size!
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*
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* there may be a few more border-cases we may need to address as well
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* but unfortunately this would mean splitting up the scatter-gather
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* list making it slightly unpractical...
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*/
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static void bcm2835_spi_dma_done(void *data)
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{
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struct spi_master *master = data;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* reset fifo and HW */
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bcm2835_spi_reset_hw(master);
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/* and terminate tx-dma as we do not have an irq for it
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* because when the rx dma will terminate and this callback
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* is called the tx-dma must have finished - can't get to this
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* situation otherwise...
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*/
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dmaengine_terminate_all(master->dma_tx);
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/* mark as no longer pending */
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bs->dma_pending = 0;
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/* and mark as completed */;
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complete(&master->xfer_completion);
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}
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static int bcm2835_spi_prepare_sg(struct spi_master *master,
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struct spi_transfer *tfr,
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bool is_tx)
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{
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struct dma_chan *chan;
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struct scatterlist *sgl;
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unsigned int nents;
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enum dma_transfer_direction dir;
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unsigned long flags;
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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if (is_tx) {
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dir = DMA_MEM_TO_DEV;
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chan = master->dma_tx;
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nents = tfr->tx_sg.nents;
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sgl = tfr->tx_sg.sgl;
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flags = 0 /* no tx interrupt */;
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} else {
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dir = DMA_DEV_TO_MEM;
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chan = master->dma_rx;
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nents = tfr->rx_sg.nents;
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sgl = tfr->rx_sg.sgl;
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flags = DMA_PREP_INTERRUPT;
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}
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/* prepare the channel */
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desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
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if (!desc)
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return -EINVAL;
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/* set callback for rx */
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if (!is_tx) {
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desc->callback = bcm2835_spi_dma_done;
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desc->callback_param = master;
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}
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/* submit it to DMA-engine */
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cookie = dmaengine_submit(desc);
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return dma_submit_error(cookie);
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}
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static inline int bcm2835_check_sg_length(struct sg_table *sgt)
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{
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int i;
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struct scatterlist *sgl;
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/* check that the sg entries are word-sized (except for last) */
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for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) {
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if (sg_dma_len(sgl) % 4)
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return -EFAULT;
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}
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return 0;
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}
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static int bcm2835_spi_transfer_one_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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u32 cs)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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int ret;
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/* check that the scatter gather segments are all a multiple of 4 */
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if (bcm2835_check_sg_length(&tfr->tx_sg) ||
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bcm2835_check_sg_length(&tfr->rx_sg)) {
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dev_warn_once(&spi->dev,
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"scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n");
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return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
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}
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/* setup tx-DMA */
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ret = bcm2835_spi_prepare_sg(master, tfr, true);
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if (ret)
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return ret;
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/* start TX early */
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dma_async_issue_pending(master->dma_tx);
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/* mark as dma pending */
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bs->dma_pending = 1;
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/* set the DMA length */
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bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len);
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/* start the HW */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
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/* setup rx-DMA late - to run transfers while
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* mapping of the rx buffers still takes place
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* this saves 10us or more.
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*/
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ret = bcm2835_spi_prepare_sg(master, tfr, false);
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if (ret) {
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/* need to reset on errors */
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dmaengine_terminate_all(master->dma_tx);
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bcm2835_spi_reset_hw(master);
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return ret;
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}
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/* start rx dma late */
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dma_async_issue_pending(master->dma_rx);
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/* wait for wakeup in framework */
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return 1;
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}
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static bool bcm2835_spi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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/* only run for gpio_cs */
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if (!gpio_is_valid(spi->cs_gpio))
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return false;
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/* we start DMA efforts only on bigger transfers */
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if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
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return false;
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/* BCM2835_SPI_DLEN has defined a max transfer size as
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* 16 bit, so max is 65535
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* we can revisit this by using an alternative transfer
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* method - ideally this would get done without any more
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* interaction...
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*/
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if (tfr->len > 65535) {
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dev_warn_once(&spi->dev,
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"transfer size of %d too big for dma-transfer\n",
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tfr->len);
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return false;
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}
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/* if we run rx/tx_buf with word aligned addresses then we are OK */
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if (((u32)tfr->tx_buf % 4 == 0) && ((u32)tfr->tx_buf % 4 == 0))
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return true;
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/* otherwise we only allow transfers within the same page
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* to avoid wasting time on dma_mapping when it is not practical
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*/
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if (((u32)tfr->tx_buf % SZ_4K) + tfr->len > SZ_4K) {
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dev_warn_once(&spi->dev,
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"Unaligned spi tx-transfer bridging page\n");
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return false;
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}
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if (((u32)tfr->rx_buf % SZ_4K) + tfr->len > SZ_4K) {
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dev_warn_once(&spi->dev,
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"Unaligned spi tx-transfer bridging page\n");
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return false;
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}
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/* return OK */
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return true;
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}
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void bcm2835_dma_release(struct spi_master *master)
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{
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if (master->dma_tx) {
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dmaengine_terminate_all(master->dma_tx);
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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}
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if (master->dma_rx) {
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dmaengine_terminate_all(master->dma_rx);
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dma_release_channel(master->dma_rx);
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master->dma_rx = NULL;
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}
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}
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void bcm2835_dma_init(struct spi_master *master, struct device *dev)
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{
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struct dma_slave_config slave_config;
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const __be32 *addr;
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dma_addr_t dma_reg_base;
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int ret;
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/* base address in dma-space */
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addr = of_get_address(master->dev.of_node, 0, NULL, NULL);
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if (!addr) {
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dev_err(dev, "could not get DMA-register address - not using dma mode\n");
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goto err;
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}
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dma_reg_base = be32_to_cpup(addr);
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/* get tx/rx dma */
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master->dma_tx = dma_request_slave_channel(dev, "tx");
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if (!master->dma_tx) {
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dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
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goto err;
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}
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master->dma_rx = dma_request_slave_channel(dev, "rx");
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if (!master->dma_rx) {
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dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
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goto err_release;
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}
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/* configure DMAs */
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slave_config.direction = DMA_MEM_TO_DEV;
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slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
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slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ret = dmaengine_slave_config(master->dma_tx, &slave_config);
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if (ret)
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goto err_config;
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slave_config.direction = DMA_DEV_TO_MEM;
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slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
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slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ret = dmaengine_slave_config(master->dma_rx, &slave_config);
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if (ret)
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goto err_config;
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/* all went well, so set can_dma */
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master->can_dma = bcm2835_spi_can_dma;
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master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */
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/* need to do TX AND RX DMA, so we need dummy buffers */
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master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
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return;
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err_config:
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dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
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ret);
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err_release:
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bcm2835_dma_release(master);
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err:
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return;
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}
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static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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@ -301,12 +582,26 @@ static int bcm2835_spi_transfer_one(struct spi_master *master,
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return bcm2835_spi_transfer_one_poll(master, spi, tfr,
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cs, xfer_time_us);
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/* run in dma mode if conditions are right */
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if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr))
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return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs);
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/* run in interrupt-mode */
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return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
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}
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static void bcm2835_spi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* if an error occurred and we have an active dma, then terminate */
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if (bs->dma_pending) {
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dmaengine_terminate_all(master->dma_tx);
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dmaengine_terminate_all(master->dma_rx);
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bs->dma_pending = 0;
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}
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/* and reset */
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bcm2835_spi_reset_hw(master);
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}
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@ -476,6 +771,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
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goto out_clk_disable;
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}
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bcm2835_dma_init(master, &pdev->dev);
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/* initialise the hardware with the default polarities */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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@ -506,6 +803,8 @@ static int bcm2835_spi_remove(struct platform_device *pdev)
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clk_disable_unprepare(bs->clk);
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bcm2835_dma_release(master);
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return 0;
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}
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