drm/amdgpu/dc: fix DCN3.1 FP handling
Missing proper DC_FP_START/DC_FP_END. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1633,7 +1633,7 @@ static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
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}
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}
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static void dcn31_calculate_wm_and_dlg(
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static void dcn31_calculate_wm_and_dlg_fp(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt,
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@ -1759,6 +1759,17 @@ static void dcn31_calculate_wm_and_dlg(
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dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
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}
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static void dcn31_calculate_wm_and_dlg(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt,
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int vlevel)
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{
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DC_FP_START();
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dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
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DC_FP_END();
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}
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static struct dc_cap_funcs cap_funcs = {
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.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
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};
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@ -1890,6 +1901,8 @@ static bool dcn31_resource_construct(
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struct dc_context *ctx = dc->ctx;
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struct irq_service_init_data init_data;
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DC_FP_START();
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ctx->dc_bios->regs = &bios_regs;
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pool->base.res_cap = &res_cap_dcn31;
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@ -2152,10 +2165,13 @@ static bool dcn31_resource_construct(
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dc->cap_funcs = cap_funcs;
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DC_FP_END();
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return true;
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create_fail:
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DC_FP_END();
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dcn31_resource_destruct(pool);
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return false;
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