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drm/i915: Switch to using DP_MSA_MISC_* defines

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Now that we have standard defines for the MSA MISC bits lets use
them on HSW+ where we program these directly into the TRANS_MSA_MISC
register.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-7-ville.syrjala@linux.intel.com
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
This commit is contained in:
Ville Syrjälä 2019-07-18 17:50:47 +03:00
parent 0299dfa7ad
commit 3e706dff08
2 changed files with 9 additions and 21 deletions
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17
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -1754,20 +1754,20 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
WARN_ON(transcoder_is_dsi(cpu_transcoder));
temp = TRANS_MSA_SYNC_CLK;
temp = DP_MSA_MISC_SYNC_CLOCK;
switch (crtc_state->pipe_bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
temp |= DP_MSA_MISC_6_BPC;
break;
case 24:
temp |= TRANS_MSA_8_BPC;
temp |= DP_MSA_MISC_8_BPC;
break;
case 30:
temp |= TRANS_MSA_10_BPC;
temp |= DP_MSA_MISC_10_BPC;
break;
case 36:
temp |= TRANS_MSA_12_BPC;
temp |= DP_MSA_MISC_12_BPC;
break;
default:
MISSING_CASE(crtc_state->pipe_bpp);
@ -1779,7 +1779,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
if (crtc_state->limited_color_range)
temp |= TRANS_MSA_CEA_RANGE;
temp |= DP_MSA_MISC_COLOR_CEA_RGB;
/*
* As per DP 1.2 spec section 2.3.4.3 while sending
@ -1787,8 +1787,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
* colorspace information.
*/
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR |
TRANS_MSA_YCBCR_BT709;
temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
/*
* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
@ -1797,7 +1796,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
*/
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
temp |= TRANS_MSA_USE_VSC_SDP;
temp |= DP_MSA_MISC_COLOR_VSC_SDP;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}

13
drivers/gpu/drm/i915/i915_reg.h
View File

@ -9759,18 +9759,7 @@ enum skl_power_gate {
#define _TRANSC_MSA_MISC 0x62410
#define _TRANS_EDP_MSA_MISC 0x6f410
#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
#define TRANS_MSA_SYNC_CLK (1 << 0)
#define TRANS_MSA_SAMPLING_444 (2 << 1)
#define TRANS_MSA_CLRSP_YCBCR (1 << 3)
#define TRANS_MSA_YCBCR_BT709 (1 << 4)
#define TRANS_MSA_6_BPC (0 << 5)
#define TRANS_MSA_8_BPC (1 << 5)
#define TRANS_MSA_10_BPC (2 << 5)
#define TRANS_MSA_12_BPC (3 << 5)
#define TRANS_MSA_16_BPC (4 << 5)
#define TRANS_MSA_CEA_RANGE (1 << 3)
#define TRANS_MSA_USE_VSC_SDP (1 << 14)
/* See DP_MSA_MISC_* for the bit definitions */
/* LCPLL Control */
#define LCPLL_CTL _MMIO(0x130040)