forked from Minki/linux
openrisc: add cache way information to cpuinfo
Motivation for this is to be able to print the way information properly in print_cpuinfo(), instead of hardcoding it to one. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Signed-off-by: Jonas Bonn <jonas@southpole.se> [shorne@gmail.com fixed conflict with show_cpuinfo change] Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -24,9 +24,11 @@ struct cpuinfo {
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u32 icache_size;
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u32 icache_block_size;
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u32 icache_ways;
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u32 dcache_size;
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u32 dcache_block_size;
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u32 dcache_ways;
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};
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extern struct cpuinfo cpuinfo;
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@ -117,13 +117,15 @@ static void print_cpuinfo(void)
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if (upr & SPR_UPR_DCP)
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printk(KERN_INFO
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"-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
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cpuinfo.dcache_size, cpuinfo.dcache_block_size, 1);
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cpuinfo.dcache_size, cpuinfo.dcache_block_size,
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cpuinfo.dcache_ways);
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else
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printk(KERN_INFO "-- dcache disabled\n");
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if (upr & SPR_UPR_ICP)
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printk(KERN_INFO
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"-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
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cpuinfo.icache_size, cpuinfo.icache_block_size, 1);
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cpuinfo.icache_size, cpuinfo.icache_block_size,
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cpuinfo.icache_ways);
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else
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printk(KERN_INFO "-- icache disabled\n");
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@ -155,25 +157,25 @@ void __init setup_cpuinfo(void)
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{
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struct device_node *cpu;
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unsigned long iccfgr, dccfgr;
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unsigned long cache_set_size, cache_ways;
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unsigned long cache_set_size;
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cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
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if (!cpu)
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panic("No compatible CPU found in device tree...\n");
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iccfgr = mfspr(SPR_ICCFGR);
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cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cpuinfo.icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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cpuinfo.icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
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cpuinfo.icache_size =
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cache_set_size * cache_ways * cpuinfo.icache_block_size;
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cache_set_size * cpuinfo.icache_ways * cpuinfo.icache_block_size;
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dccfgr = mfspr(SPR_DCCFGR);
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cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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cpuinfo.dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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cpuinfo.dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
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cpuinfo.dcache_size =
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cache_set_size * cache_ways * cpuinfo.dcache_block_size;
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cache_set_size * cpuinfo.dcache_ways * cpuinfo.dcache_block_size;
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if (of_property_read_u32(cpu, "clock-frequency",
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&cpuinfo.clock_frequency)) {
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@ -308,30 +310,33 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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revision = vr & SPR_VR_REV;
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seq_printf(m,
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"cpu\t\t: OpenRISC-%x\n"
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"revision\t: %d\n"
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"frequency\t: %ld\n"
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"dcache size\t: %d bytes\n"
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"dcache block size\t: %d bytes\n"
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"icache size\t: %d bytes\n"
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"icache block size\t: %d bytes\n"
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"immu\t\t: %d entries, %lu ways\n"
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"dmmu\t\t: %d entries, %lu ways\n"
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"bogomips\t: %lu.%02lu\n",
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version,
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revision,
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loops_per_jiffy * HZ,
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cpuinfo.dcache_size,
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cpuinfo.dcache_block_size,
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cpuinfo.icache_size,
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cpuinfo.icache_block_size,
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1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
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1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
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1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
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1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
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(loops_per_jiffy * HZ) / 500000,
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((loops_per_jiffy * HZ) / 5000) % 100);
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"cpu\t\t: OpenRISC-%x\n"
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"revision\t: %d\n"
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"frequency\t: %ld\n"
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"dcache size\t: %d bytes\n"
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"dcache block size\t: %d bytes\n"
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"dcache ways\t: %d\n"
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"icache size\t: %d bytes\n"
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"icache block size\t: %d bytes\n"
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"icache ways\t: %d\n"
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"immu\t\t: %d entries, %lu ways\n"
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"dmmu\t\t: %d entries, %lu ways\n"
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"bogomips\t: %lu.%02lu\n",
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version,
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revision,
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loops_per_jiffy * HZ,
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cpuinfo.dcache_size,
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cpuinfo.dcache_block_size,
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cpuinfo.dcache_ways,
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cpuinfo.icache_size,
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cpuinfo.icache_block_size,
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cpuinfo.icache_ways,
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1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
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1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
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1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
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1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
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(loops_per_jiffy * HZ) / 500000,
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((loops_per_jiffy * HZ) / 5000) % 100);
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return 0;
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}
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