forked from Minki/linux
viafb: Add a simple VX855 DMA engine driver
This code provides a minimal amount of access to the DMA engine as needed by the camera driver. VX855 only; it's guaranteed not to work on other chipsets, so it won't try. Cc: ScottFang@viatech.com.cn Cc: JosephChan@via.com.tw Cc: Harald Welte <laforge@gnumonks.org> Acked-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
This commit is contained in:
Jonathan Corbet
parent
94dd1a856b
commit
3d28eb42c5
@ -13,6 +13,7 @@
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#include "global.h"
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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/*
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@ -92,7 +93,238 @@ void viafb_irq_disable(u32 mask)
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}
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EXPORT_SYMBOL_GPL(viafb_irq_disable);
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/* ---------------------------------------------------------------------- */
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/*
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* Access to the DMA engine. This currently provides what the camera
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* driver needs (i.e. outgoing only) but is easily expandable if need
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* be.
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*/
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/*
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* There are four DMA channels in the vx855. For now, we only
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* use one of them, though. Most of the time, the DMA channel
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* will be idle, so we keep the IRQ handler unregistered except
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* when some subsystem has indicated an interest.
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*/
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static int viafb_dma_users;
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static DECLARE_COMPLETION(viafb_dma_completion);
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/*
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* This mutex protects viafb_dma_users and our global interrupt
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* registration state; it also serializes access to the DMA
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* engine.
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*/
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static DEFINE_MUTEX(viafb_dma_lock);
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/*
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* The VX855 DMA descriptor (used for s/g transfers) looks
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* like this.
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*/
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struct viafb_vx855_dma_descr {
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u32 addr_low; /* Low part of phys addr */
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u32 addr_high; /* High 12 bits of addr */
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u32 fb_offset; /* Offset into FB memory */
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u32 seg_size; /* Size, 16-byte units */
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u32 tile_mode; /* "tile mode" setting */
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u32 next_desc_low; /* Next descriptor addr */
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u32 next_desc_high;
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u32 pad; /* Fill out to 64 bytes */
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};
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/*
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* Flags added to the "next descriptor low" pointers
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*/
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#define VIAFB_DMA_MAGIC 0x01 /* ??? Just has to be there */
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#define VIAFB_DMA_FINAL_SEGMENT 0x02 /* Final segment */
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/*
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* The completion IRQ handler.
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*/
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static irqreturn_t viafb_dma_irq(int irq, void *data)
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{
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int csr;
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irqreturn_t ret = IRQ_NONE;
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spin_lock(&global_dev.reg_lock);
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csr = viafb_mmio_read(VDMA_CSR0);
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if (csr & VDMA_C_DONE) {
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viafb_mmio_write(VDMA_CSR0, VDMA_C_DONE);
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complete(&viafb_dma_completion);
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ret = IRQ_HANDLED;
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}
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spin_unlock(&global_dev.reg_lock);
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return ret;
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}
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/*
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* Indicate a need for DMA functionality.
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*/
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int viafb_request_dma(void)
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{
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int ret = 0;
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/*
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* Only VX855 is supported currently.
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*/
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if (global_dev.chip_type != UNICHROME_VX855)
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return -ENODEV;
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/*
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* Note the new user and set up our interrupt handler
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* if need be.
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*/
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mutex_lock(&viafb_dma_lock);
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viafb_dma_users++;
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if (viafb_dma_users == 1) {
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ret = request_irq(global_dev.pdev->irq, viafb_dma_irq,
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IRQF_SHARED, "via-dma", &viafb_dma_users);
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if (ret)
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viafb_dma_users--;
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else
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viafb_irq_enable(VDE_I_DMA0TDEN);
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}
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mutex_unlock(&viafb_dma_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(viafb_request_dma);
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void viafb_release_dma(void)
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{
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mutex_lock(&viafb_dma_lock);
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viafb_dma_users--;
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if (viafb_dma_users == 0) {
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viafb_irq_disable(VDE_I_DMA0TDEN);
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free_irq(global_dev.pdev->irq, &viafb_dma_users);
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}
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mutex_unlock(&viafb_dma_lock);
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}
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EXPORT_SYMBOL_GPL(viafb_release_dma);
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#if 0
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/*
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* Copy a single buffer from FB memory, synchronously. This code works
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* but is not currently used.
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*/
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void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len)
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{
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unsigned long flags;
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int csr;
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mutex_lock(&viafb_dma_lock);
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init_completion(&viafb_dma_completion);
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/*
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* Program the controller.
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*/
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spin_lock_irqsave(&global_dev.reg_lock, flags);
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viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_DONE);
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/* Enable ints; must happen after CSR0 write! */
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viafb_mmio_write(VDMA_MR0, VDMA_MR_TDIE);
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viafb_mmio_write(VDMA_MARL0, (int) (paddr & 0xfffffff0));
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viafb_mmio_write(VDMA_MARH0, (int) ((paddr >> 28) & 0xfff));
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/* Data sheet suggests DAR0 should be <<4, but it lies */
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viafb_mmio_write(VDMA_DAR0, offset);
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viafb_mmio_write(VDMA_DQWCR0, len >> 4);
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viafb_mmio_write(VDMA_TMR0, 0);
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viafb_mmio_write(VDMA_DPRL0, 0);
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viafb_mmio_write(VDMA_DPRH0, 0);
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viafb_mmio_write(VDMA_PMR0, 0);
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csr = viafb_mmio_read(VDMA_CSR0);
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viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_START);
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spin_unlock_irqrestore(&global_dev.reg_lock, flags);
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/*
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* Now we just wait until the interrupt handler says
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* we're done.
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*/
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wait_for_completion_interruptible(&viafb_dma_completion);
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viafb_mmio_write(VDMA_MR0, 0); /* Reset int enable */
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mutex_unlock(&viafb_dma_lock);
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}
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EXPORT_SYMBOL_GPL(viafb_dma_copy_out);
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#endif
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/*
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* Do a scatter/gather DMA copy from FB memory. You must have done
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* a successful call to viafb_request_dma() first.
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*/
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int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg)
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{
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struct viafb_vx855_dma_descr *descr;
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void *descrpages;
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dma_addr_t descr_handle;
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unsigned long flags;
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int i;
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struct scatterlist *sgentry;
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dma_addr_t nextdesc;
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/*
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* Get a place to put the descriptors.
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*/
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descrpages = dma_alloc_coherent(&global_dev.pdev->dev,
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nsg*sizeof(struct viafb_vx855_dma_descr),
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&descr_handle, GFP_KERNEL);
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if (descrpages == NULL) {
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dev_err(&global_dev.pdev->dev, "Unable to get descr page.\n");
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return -ENOMEM;
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}
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mutex_lock(&viafb_dma_lock);
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/*
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* Fill them in.
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*/
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descr = descrpages;
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nextdesc = descr_handle + sizeof(struct viafb_vx855_dma_descr);
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for_each_sg(sg, sgentry, nsg, i) {
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dma_addr_t paddr = sg_dma_address(sgentry);
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descr->addr_low = paddr & 0xfffffff0;
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descr->addr_high = ((u64) paddr >> 32) & 0x0fff;
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descr->fb_offset = offset;
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descr->seg_size = sg_dma_len(sgentry) >> 4;
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descr->tile_mode = 0;
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descr->next_desc_low = (nextdesc&0xfffffff0) | VIAFB_DMA_MAGIC;
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descr->next_desc_high = ((u64) nextdesc >> 32) & 0x0fff;
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descr->pad = 0xffffffff; /* VIA driver does this */
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offset += sg_dma_len(sgentry);
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nextdesc += sizeof(struct viafb_vx855_dma_descr);
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descr++;
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}
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descr[-1].next_desc_low = VIAFB_DMA_FINAL_SEGMENT|VIAFB_DMA_MAGIC;
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/*
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* Program the engine.
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*/
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spin_lock_irqsave(&global_dev.reg_lock, flags);
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init_completion(&viafb_dma_completion);
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viafb_mmio_write(VDMA_DQWCR0, 0);
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viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_DONE);
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viafb_mmio_write(VDMA_MR0, VDMA_MR_TDIE | VDMA_MR_CHAIN);
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viafb_mmio_write(VDMA_DPRL0, descr_handle | VIAFB_DMA_MAGIC);
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viafb_mmio_write(VDMA_DPRH0,
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(((u64)descr_handle >> 32) & 0x0fff) | 0xf0000);
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(void) viafb_mmio_read(VDMA_CSR0);
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viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_START);
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spin_unlock_irqrestore(&global_dev.reg_lock, flags);
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/*
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* Now we just wait until the interrupt handler says
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* we're done. Except that, actually, we need to wait a little
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* longer: the interrupts seem to jump the gun a little and we
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* get corrupted frames sometimes.
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*/
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wait_for_completion_timeout(&viafb_dma_completion, 1);
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msleep(1);
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if ((viafb_mmio_read(VDMA_CSR0)&VDMA_C_DONE) == 0)
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printk(KERN_ERR "VIA DMA timeout!\n");
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/*
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* Clean up and we're done.
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*/
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viafb_mmio_write(VDMA_CSR0, VDMA_C_DONE);
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viafb_mmio_write(VDMA_MR0, 0); /* Reset int enable */
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mutex_unlock(&viafb_dma_lock);
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dma_free_coherent(&global_dev.pdev->dev,
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nsg*sizeof(struct viafb_vx855_dma_descr), descrpages,
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descr_handle);
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return 0;
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}
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EXPORT_SYMBOL_GPL(viafb_dma_copy_out_sg);
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/* ---------------------------------------------------------------------- */
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/*
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* Figure out how big our framebuffer memory is. Kind of ugly,
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* but evidently we can't trust the information found in the
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@ -131,4 +131,33 @@ void viafb_irq_disable(u32 mask);
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#define VDE_I_LVDSSIEN 0x40000000 /* LVDS Sense enable */
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#define VDE_I_ENABLE 0x80000000 /* Global interrupt enable */
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/*
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* DMA management.
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*/
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int viafb_request_dma(void);
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void viafb_release_dma(void);
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/* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
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int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
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/*
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* DMA Controller registers.
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*/
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#define VDMA_MR0 0xe00 /* Mod reg 0 */
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#define VDMA_MR_CHAIN 0x01 /* Chaining mode */
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#define VDMA_MR_TDIE 0x02 /* Transfer done int enable */
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#define VDMA_CSR0 0xe04 /* Control/status */
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#define VDMA_C_ENABLE 0x01 /* DMA Enable */
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#define VDMA_C_START 0x02 /* Start a transfer */
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#define VDMA_C_ABORT 0x04 /* Abort a transfer */
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#define VDMA_C_DONE 0x08 /* Transfer is done */
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#define VDMA_MARL0 0xe20 /* Mem addr low */
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#define VDMA_MARH0 0xe24 /* Mem addr high */
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#define VDMA_DAR0 0xe28 /* Device address */
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#define VDMA_DQWCR0 0xe2c /* Count (16-byte) */
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#define VDMA_TMR0 0xe30 /* Tile mode reg */
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#define VDMA_DPRL0 0xe34 /* Not sure */
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#define VDMA_DPR_IN 0x08 /* Inbound transfer to FB */
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#define VDMA_DPRH0 0xe38
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#define VDMA_PMR0 (0xe00 + 0x134) /* Pitch mode */
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#endif /* __VIA_CORE_H__ */
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