forked from Minki/linux
powerpc: Start merging 64-bit support into powermac files
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras
parent
e574d238ab
commit
3c3f42d63a
@ -1,8 +1,5 @@
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/*
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* Support for PCI bridges found on Power Macintoshes.
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* At present the "bandit" and "chaos" bridges are supported.
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* Fortunately you access configuration space in the same
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* way with either bridge.
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*
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* Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
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* Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
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@ -26,6 +23,10 @@
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#ifdef CONFIG_PPC64
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#include <asm/iommu.h>
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#include <asm/ppc-pci.h>
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#endif
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#undef DEBUG
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@ -160,9 +161,13 @@ static unsigned long macrisc_cfg_access(struct pci_controller* hose,
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static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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@ -187,9 +192,13 @@ static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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@ -221,7 +230,7 @@ static struct pci_ops macrisc_pci_ops =
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};
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/*
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* Verifiy that a specific (bus, dev_fn) exists on chaos
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* Verify that a specific (bus, dev_fn) exists on chaos
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*/
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static int
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chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
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@ -274,7 +283,6 @@ static struct pci_ops chaos_pci_ops =
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};
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#ifdef CONFIG_POWER4
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/*
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* These versions of U3 HyperTransport config space access ops do not
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* implement self-view of the HT host yet
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@ -342,11 +350,11 @@ static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose;
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unsigned long addr;
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struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
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if (np == NULL)
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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@ -357,19 +365,19 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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case 0:
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break;
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case 1:
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switch (len) {
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case 1:
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*val = 0xff; break;
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case 2:
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*val = 0xffff; break;
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default:
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*val = 0xfffffffful; break;
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}
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return PCIBIOS_SUCCESSFUL;
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switch (len) {
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case 1:
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*val = 0xff; break;
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case 2:
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*val = 0xffff; break;
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default:
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*val = 0xfffffffful; break;
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}
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return PCIBIOS_SUCCESSFUL;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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@ -391,11 +399,11 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose;
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unsigned long addr;
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struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
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if (np == NULL)
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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@ -437,15 +445,13 @@ static struct pci_ops u3_ht_pci_ops =
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u3_ht_read_config,
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u3_ht_write_config
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};
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#endif /* CONFIG_POWER4 */
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/*
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* For a bandit bridge, turn on cache coherency if necessary.
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* N.B. we could clean this up using the hose ops directly.
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*/
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static void __init
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init_bandit(struct pci_controller *bp)
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static void __init init_bandit(struct pci_controller *bp)
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{
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unsigned int vendev, magic;
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int rev;
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@ -485,8 +491,7 @@ init_bandit(struct pci_controller *bp)
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/*
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* Tweak the PCI-PCI bridge chip on the blue & white G3s.
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*/
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static void __init
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init_p2pbridge(void)
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static void __init init_p2pbridge(void)
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{
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struct device_node *p2pbridge;
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struct pci_controller* hose;
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@ -526,8 +531,7 @@ init_p2pbridge(void)
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* EHCI part of it so it behaves like a pair of OHCI's. This fixup
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* code re-enables it ;)
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*/
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static void __init
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fixup_nec_usb2(void)
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static void __init fixup_nec_usb2(void)
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{
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struct device_node *nec;
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@ -567,77 +571,6 @@ fixup_nec_usb2(void)
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}
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}
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void __init
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pmac_find_bridges(void)
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{
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struct device_node *np, *root;
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struct device_node *ht = NULL;
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root = of_find_node_by_path("/");
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if (root == NULL) {
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printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
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return;
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}
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for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
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if (np->name == NULL)
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continue;
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if (strcmp(np->name, "bandit") == 0
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|| strcmp(np->name, "chaos") == 0
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|| strcmp(np->name, "pci") == 0) {
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if (add_bridge(np) == 0)
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of_node_get(np);
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}
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if (strcmp(np->name, "ht") == 0) {
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of_node_get(np);
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ht = np;
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}
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}
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of_node_put(root);
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/* Probe HT last as it relies on the agp resources to be already
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* setup
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*/
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if (ht && add_bridge(ht) != 0)
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of_node_put(ht);
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init_p2pbridge();
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fixup_nec_usb2();
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/* We are still having some issues with the Xserve G4, enabling
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* some offset between bus number and domains for now when we
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* assign all busses should help for now
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*/
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if (pci_assign_all_busses)
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pcibios_assign_bus_offset = 0x10;
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#ifdef CONFIG_POWER4
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/* There is something wrong with DMA on U3/HT. I haven't figured out
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* the details yet, but if I set the cache line size to 128 bytes like
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* it should, I'm getting memory corruption caused by devices like
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* sungem (even without the MWI bit set, but maybe sungem doesn't
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* care). Right now, it appears that setting up a 64 bytes line size
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* works properly, 64 bytes beeing the max transfer size of HT, I
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* suppose this is related the way HT/PCI are hooked together. I still
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* need to dive into more specs though to be really sure of what's
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* going on. --BenH.
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*
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* Ok, apparently, it's just that HT can't do more than 64 bytes
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* transactions. MWI seem to be meaningless there as well, it may
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* be worth nop'ing out pci_set_mwi too though I haven't done that
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* yet.
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*
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* Note that it's a bit different for whatever is in the AGP slot.
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* For now, I don't care, but this can become a real issue, we
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* should probably hook pci_set_mwi anyway to make sure it sets
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* the real cache line size in there.
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*/
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if (machine_is_compatible("MacRISC4"))
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pci_cache_line_size = 16; /* 64 bytes */
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pmac_check_ht_link();
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#endif /* CONFIG_POWER4 */
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}
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#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
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| (((o) & ~3) << 24))
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@ -703,7 +636,6 @@ setup_chaos(struct pci_controller* hose, struct reg_property* addr)
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}
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#ifdef CONFIG_POWER4
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static void __init setup_u3_agp(struct pci_controller* hose)
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{
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/* On G5, we move AGP up to high bus number so we don't need
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@ -715,7 +647,7 @@ static void __init setup_u3_agp(struct pci_controller* hose)
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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*/
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hose->first_busno = 0xf0;
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hose->first_busno = 0xf0;
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hose->last_busno = 0xff;
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has_uninorth = 1;
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hose->ops = ¯isc_pci_ops;
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@ -748,7 +680,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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*/
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hose->io_base_phys = 0xf4000000;
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hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
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isa_io_base = (unsigned long) hose->io_base_virt;
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isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
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hose->io_resource.name = np->full_name;
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hose->io_resource.start = 0;
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hose->io_resource.end = 0x003fffff;
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@ -794,13 +726,13 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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}
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/* No, it's not the case, we need a hole */
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if (cur == 2) {
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/* not enough resources to make a hole, we drop part of the range */
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/* not enough resources for a hole, we drop part of the range */
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printk(KERN_WARNING "Running out of resources for /ht host !\n");
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hose->mem_resources[cur].end = res->start - 1;
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continue;
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}
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cur++;
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DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
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DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
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cur-1, res->start - 1, cur, res->end + 1);
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hose->mem_resources[cur].name = np->full_name;
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hose->mem_resources[cur].flags = IORESOURCE_MEM;
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@ -981,7 +913,7 @@ static int __init add_bridge(struct device_node *dev)
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if (device_is_compatible(dev, "uni-north")) {
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primary = setup_uninorth(hose, addr);
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disp_name = "UniNorth";
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} else if (strcmp(dev->name, "pci") == 0) {
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} else if (strcmp(dev->name, "pci") == 0) {
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/* XXX assume this is a mpc106 (grackle) */
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setup_grackle(hose);
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disp_name = "Grackle (MPC106)";
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@ -993,7 +925,7 @@ static int __init add_bridge(struct device_node *dev)
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disp_name = "Chaos";
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primary = 0;
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}
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printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
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printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. Firmware bus number: %d->%d\n",
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disp_name, addr->address, hose->first_busno, hose->last_busno);
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DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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@ -1036,6 +968,50 @@ pmac_pcibios_fixup(void)
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pcibios_fixup_OF_interrupts();
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}
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void __init pmac_find_bridges(void)
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{
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struct device_node *np, *root;
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struct device_node *ht = NULL;
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root = of_find_node_by_path("/");
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if (root == NULL) {
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printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
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return;
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}
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for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
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if (np->name == NULL)
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continue;
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if (strcmp(np->name, "bandit") == 0
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|| strcmp(np->name, "chaos") == 0
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|| strcmp(np->name, "pci") == 0) {
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if (add_bridge(np) == 0)
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of_node_get(np);
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}
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if (strcmp(np->name, "ht") == 0) {
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of_node_get(np);
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ht = np;
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}
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}
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of_node_put(root);
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/* Probe HT last as it relies on the agp resources to be already
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* setup
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*/
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if (ht && add_bridge(ht) != 0)
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of_node_put(ht);
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init_p2pbridge();
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fixup_nec_usb2();
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/* We are still having some issues with the Xserve G4, enabling
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* some offset between bus number and domains for now when we
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* assign all busses should help for now
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*/
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if (pci_assign_all_busses)
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pcibios_assign_bus_offset = 0x10;
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}
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int
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pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
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{
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@ -25,6 +25,7 @@
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#include <linux/sysdev.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/module.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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@ -32,12 +33,11 @@
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/open_pic.h>
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#include <asm/xmon.h>
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#include <asm/pmac_feature.h>
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#include <asm/mpic.h>
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#include "pmac_pic.h"
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#include "pmac.h"
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/*
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* XXX this should be in xmon.h, but putting it there means xmon.h
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@ -46,6 +46,7 @@
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*/
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extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
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#ifdef CONFIG_PPC32
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struct pmac_irq_hw {
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unsigned int event;
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unsigned int enable;
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@ -71,6 +72,9 @@ static u32 level_mask[4];
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static DEFINE_SPINLOCK(pmac_pic_lock);
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/* XXX here for now, should move to arch/powerpc/kernel/irq.c */
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int ppc_do_canonicalize_irqs;
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EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
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#define GATWICK_IRQ_POOL_SIZE 10
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static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
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@ -377,11 +381,6 @@ static int __init enable_second_ohare(void)
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return irqctrler->intrs[0].line;
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}
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static int pmac_u3_cascade(struct pt_regs *regs, void *data)
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{
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return mpic_get_one_irq((struct mpic *)data, regs);
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}
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#ifdef CONFIG_XMON
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static struct irqaction xmon_action = {
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.handler = xmon_irq,
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@ -397,15 +396,23 @@ static struct irqaction gatwick_cascade_action = {
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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#endif /* CONFIG_PPC32 */
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static int pmac_u3_cascade(struct pt_regs *regs, void *data)
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{
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return mpic_get_one_irq((struct mpic *)data, regs);
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}
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void __init pmac_pic_init(void)
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{
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int i;
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struct device_node *irqctrler = NULL;
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struct device_node *irqctrler2 = NULL;
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struct device_node *np;
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#ifdef CONFIG_PPC32
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int i;
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unsigned long addr;
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int irq_cascade = -1;
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#endif
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struct mpic *mpic1, *mpic2;
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/* We first try to detect Apple's new Core99 chipset, since mac-io
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@ -455,7 +462,7 @@ void __init pmac_pic_init(void)
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mpic_setup_cascade(irqctrler2->intrs[0].line,
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pmac_u3_cascade, mpic2);
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}
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#ifdef CONFIG_XMON
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#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
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{
|
||||
struct device_node* pswitch;
|
||||
int nmi_irq;
|
||||
@ -463,7 +470,7 @@ void __init pmac_pic_init(void)
|
||||
pswitch = find_devices("programmer-switch");
|
||||
if (pswitch && pswitch->n_intrs) {
|
||||
nmi_irq = pswitch->intrs[0].line;
|
||||
openpic_init_nmi_irq(nmi_irq);
|
||||
mpic_irq_set_priority(nmi_irq, 9);
|
||||
setup_irq(nmi_irq, &xmon_action);
|
||||
}
|
||||
}
|
||||
@ -472,6 +479,7 @@ void __init pmac_pic_init(void)
|
||||
}
|
||||
irqctrler = NULL;
|
||||
|
||||
#ifdef CONFIG_PPC32
|
||||
/* Get the level/edge settings, assume if it's not
|
||||
* a Grand Central nor an OHare, then it's an Heathrow
|
||||
* (or Paddington).
|
||||
@ -570,6 +578,7 @@ void __init pmac_pic_init(void)
|
||||
#ifdef CONFIG_XMON
|
||||
setup_irq(20, &xmon_action);
|
||||
#endif /* CONFIG_XMON */
|
||||
#endif /* CONFIG_PPC32 */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
@ -659,9 +668,10 @@ static struct sysdev_driver driver_pmacpic = {
|
||||
|
||||
static int __init init_pmacpic_sysfs(void)
|
||||
{
|
||||
#ifdef CONFIG_PPC32
|
||||
if (max_irqs == 0)
|
||||
return -ENODEV;
|
||||
|
||||
#endif
|
||||
printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
|
||||
sysdev_class_register(&pmacpic_sysclass);
|
||||
sysdev_register(&device_pmacpic);
|
||||
|
||||
@ -3,19 +3,31 @@
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ide.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
/*
|
||||
* Declaration for the various functions exported by the
|
||||
* pmac_* files. Mostly for use by pmac_setup
|
||||
*/
|
||||
|
||||
extern void pmac_get_boot_time(struct rtc_time *tm);
|
||||
extern void pmac_get_rtc_time(struct rtc_time *tm);
|
||||
extern int pmac_set_rtc_time(struct rtc_time *tm);
|
||||
extern long pmac_time_init(void);
|
||||
extern unsigned long pmac_get_rtc_time(void);
|
||||
extern int pmac_set_rtc_time(unsigned long nowtime);
|
||||
extern void pmac_read_rtc_time(void);
|
||||
extern void pmac_calibrate_decr(void);
|
||||
|
||||
extern void pmac_pcibios_fixup(void);
|
||||
extern void pmac_find_bridges(void);
|
||||
extern unsigned long pmac_ide_get_base(int index);
|
||||
extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
|
||||
unsigned long data_port, unsigned long ctrl_port, int *irq);
|
||||
|
||||
extern void pmac_nvram_update(void);
|
||||
extern unsigned char pmac_nvram_read_byte(int addr);
|
||||
extern void pmac_nvram_write_byte(int addr, unsigned char val);
|
||||
extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial);
|
||||
extern void pmac_pcibios_after_init(void);
|
||||
extern int of_show_percpuinfo(struct seq_file *m, int i);
|
||||
|
||||
extern void pmac_pci_init(void);
|
||||
extern void pmac_setup_pci_dma(void);
|
||||
extern void pmac_check_ht_link(void);
|
||||
@ -28,4 +40,9 @@ extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
|
||||
|
||||
extern void pmac_nvram_init(void);
|
||||
|
||||
extern struct hw_interrupt_type pmac_pic;
|
||||
|
||||
void pmac_pic_init(void);
|
||||
int pmac_get_irq(struct pt_regs *regs);
|
||||
|
||||
#endif /* __PMAC_H__ */
|
||||
|
||||
@ -73,28 +73,10 @@
|
||||
#include <asm/of_device.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
#include "pmac_pic.h"
|
||||
#include "pmac.h"
|
||||
|
||||
#undef SHOW_GATWICK_IRQS
|
||||
|
||||
extern long pmac_time_init(void);
|
||||
extern unsigned long pmac_get_rtc_time(void);
|
||||
extern int pmac_set_rtc_time(unsigned long nowtime);
|
||||
extern void pmac_read_rtc_time(void);
|
||||
extern void pmac_calibrate_decr(void);
|
||||
extern void pmac_pcibios_fixup(void);
|
||||
extern void pmac_find_bridges(void);
|
||||
extern unsigned long pmac_ide_get_base(int index);
|
||||
extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
|
||||
unsigned long data_port, unsigned long ctrl_port, int *irq);
|
||||
|
||||
extern void pmac_nvram_update(void);
|
||||
extern unsigned char pmac_nvram_read_byte(int addr);
|
||||
extern void pmac_nvram_write_byte(int addr, unsigned char val);
|
||||
extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial);
|
||||
extern void pmac_pcibios_after_init(void);
|
||||
extern int of_show_percpuinfo(struct seq_file *m, int i);
|
||||
|
||||
unsigned char drive_info;
|
||||
|
||||
int ppc_override_l2cr = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user