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clk: renesas: rcar-gen3: Rename DRIF clocks

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According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

    DRIF0 to DRIF00
    DRIF1 to DRIF01
    DRIF2 to DRIF10
    DRIF3 to DRIF11
    DRIF4 to DRIF20
    DRIF5 to DRIF21
    DRIF6 to DRIF30
    DRIF7 to DRIF31

Therefore, this patch renames the DRIF clocks from DRIFn to DRIFmm.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Takeshi Kihara 2019-03-08 20:53:19 +09:00 committed by Geert Uytterhoeven
parent b9df2ea2b8
commit 3c14505c68
4 changed files with 35 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -3,7 +3,7 @@
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on clk-rcar-gen3.c
*
@ -156,14 +156,14 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),

16
drivers/clk/renesas/r8a7796-cpg-mssr.c
View File

@ -149,14 +149,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),

17
drivers/clk/renesas/r8a77965-cpg-mssr.c
View File

@ -3,6 +3,7 @@
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
* Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@ -148,14 +149,14 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),

18
drivers/clk/renesas/r8a77990-cpg-mssr.c
View File

@ -2,7 +2,7 @@
/*
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@ -154,14 +154,14 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),