IXP4xx DTS updates for the v5.14 kernel:
- Add ethernet to the boards - Add PCI hosts to the boards - Create an expansion bus around the flash memory - Add the beeper to NSLU2 completing the NSLU2 DTS -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmC2GpQACgkQQRCzN7AZ XXM+rBAAi4pY5gcmzy3tFdt0wNuJFs3Wn8zvaWRybFottIvfUw+lXOYiHBpa9O0m yToj+LwKbylgeAuG7rfjzVRq0snKKF5y00eq3MKPGxYTZYGQ71lw80v24k6hnxug yOKzabbViQihHPzddxZmPvjI8jFjZlx4ChHIe1rbzRxQgfR1uqaKICuaake7/jXr PEoP4uhfyIjBuOiCBBva3UPhSKuEZUJnzOGs0TbYoX8D3DryWQrCtWVg0ogWwdWM /SLjFpuHpsYt84d8wIkMPu8sVcrj0/jy796UISPhKYxMKMd8USzkAZcyxD3w/WNJ KjtQnp137smEoeqqLnHViEqMD7jv7GG0+ptfhMqRGKiV770yOKbXKvCj/EWQxIfX wjdLesSIa8douAk6jX09iSaVril+oxw9fNCsRJJX5k0382quGEvjZPfhs3qSuL8Q ltXB/y5hV9ropbvi2volRvx5PF54RNFCxJW68fAaV8FxNhOOUGDLWp3fQ7oDl2Iz EOEgqeu/Ue1wffrZ+tJWQDn6z04Yj7vs/76YzaRicc8JIr4o8rS+6f9feYLYSDgQ K8LZaKUhS7XHR4YMzWqNi0oIsT2T1JIWWtO16JYvk1pRIbIgVAaiztXPeZcGkHs4 jIyIMIJ8FpnQYmMvbtT7jOVCVSdLenrHVKjfitgKI4uGqtRj2fg= =W/eR -----END PGP SIGNATURE----- Merge tag 'ixp4xx-dts-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt IXP4xx DTS updates for the v5.14 kernel: - Add ethernet to the boards - Add PCI hosts to the boards - Create an expansion bus around the flash memory - Add the beeper to NSLU2 completing the NSLU2 DTS * tag 'ixp4xx-dts-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: Fix up the IXP4xx ethernet nodes ARM: dts: ixp4xx: Add beeper to the NSLU2 ARM: dts: ixp4xx: Create a proper expansion bus ARM: dts: ixp4xx: Add PCI hosts ARM: dts: ixp4xx: Add ethernet Link: https://lore.kernel.org/r/CACRpkdbmRjGW7vpr7hG+jiRTqNMZAyKZNhtvzj=SqhZmb1+F6A@mail.gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
3b0898f978
@ -90,20 +90,71 @@
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timeout-ms = <5000>;
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};
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/* The first 16MB region on the expansion bus */
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flash@50000000 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 8 MB of Flash in 0x20000 byte blocks
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* mapped in at 0x50000000
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*/
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reg = <0x50000000 0x800000>;
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gpio-beeper {
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compatible = "gpio-beeper";
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gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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};
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x7e0000 */
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fis-index-block = <0x3f>;
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soc {
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bus@50000000 {
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/* The first 16MB region at CS0 on the expansion bus */
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flash@0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 8 MB of Flash in 0x20000 byte blocks
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* mapped in at CS0.
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*/
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reg = <0x00000000 0x800000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x7e0000 */
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fis-index-block = <0x3f>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
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* We have slots (IDSEL) 1, 2 and 3.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
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<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
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<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
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<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
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<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
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<0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
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<0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
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/* IDSEL 3 */
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<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
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<0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
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<0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
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<0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
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};
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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};
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};
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@ -7,6 +7,10 @@
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/ {
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soc {
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pci@c0000000 {
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compatible = "intel,ixp42x-pci";
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};
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interrupt-controller@c8003000 {
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compatible = "intel,ixp42x-interrupt";
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};
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@ -76,19 +76,97 @@
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};
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};
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flash@50000000 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 32 MB of Flash in 0x20000 byte blocks
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* mapped in at 0x50000000
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*/
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reg = <0x50000000 0x2000000>;
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soc {
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bus@50000000 {
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flash@0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 32 MB of Flash in 0x20000 byte blocks
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* mapped in at CS0.
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*/
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reg = <0x00000000 0x2000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x1fe0000 */
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fis-index-block = <0xff>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x1fe0000 */
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fis-index-block = <0xff>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* In the boardfile for the Cambria from OpenWRT the interrupts
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* are assigned one per IDSEL, so all 4 interrupts from IDSEL
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* 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
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* connected to IRQ 10 etc. I find this highly unlikely so I
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* have instead assumed that they are rotated (swizzled) like
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* this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
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<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
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<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
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<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
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<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
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<0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
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<0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
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/* IDSEL 3 */
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<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
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<0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
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<0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
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<0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
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/* IDSEL 4 */
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<0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
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<0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
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<0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
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<0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
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/* IDSEL 6 */
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<0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
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<0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
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<0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
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<0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
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/* IDSEL 15 */
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<0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
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<0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
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<0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
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<0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
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};
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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};
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};
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ethernet@c800c000 {
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status = "ok";
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queue-rx = <&qmgr 2>;
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queue-txready = <&qmgr 19>;
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phy-mode = "rgmii";
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phy-handle = <&phy2>;
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intel,npe-handle = <&npe 0>;
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};
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};
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};
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@ -8,6 +8,10 @@
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/ {
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soc {
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pci@c0000000 {
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compatible = "intel,ixp43x-pci";
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};
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interrupt-controller@c8003000 {
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compatible = "intel,ixp43x-interrupt";
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};
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@ -30,5 +30,38 @@
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interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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/* This is known as EthB1 */
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ethernet@c800d000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc800d000 0x1000>;
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status = "disabled";
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intel,npe = <1>;
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 0>;
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queue-txready = <&qmgr 0>;
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};
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/* This is known as EthB2 */
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ethernet@c800e000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc800e000 0x1000>;
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status = "disabled";
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intel,npe = <2>;
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 0>;
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queue-txready = <&qmgr 0>;
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};
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/* This is known as EthB3 */
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ethernet@c800f000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc800f000 0x1000>;
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status = "disabled";
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intel,npe = <3>;
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 0>;
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queue-txready = <&qmgr 0>;
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};
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};
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};
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@ -14,12 +14,61 @@
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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/*
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* The IXP4xx expansion bus is a set of 16 or 32MB
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* windows in the 256MB space from 0x50000000 to
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* 0x5fffffff.
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*/
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bus@50000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x50000000 0x10000000>;
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dma-ranges = <0x00000000 0x50000000 0x10000000>;
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};
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qmgr: queue-manager@60000000 {
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compatible = "intel,ixp4xx-ahb-queue-manager";
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reg = <0x60000000 0x4000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci@c0000000 {
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/* compatible filled in by per-soc device tree */
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reg = <0xc0000000 0x1000>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
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<9 IRQ_TYPE_LEVEL_HIGH>,
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<10 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x00 0xff>;
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status = "disabled";
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ranges =
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/*
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* 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
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* done in 4 chunks of 16MB each.
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*/
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<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
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/* 64KB I/O space at 0x4c000000 */
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<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
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/*
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* This needs to map to the start of physical memory so
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* PCI devices can see all (hopefully) memory. This is done
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* using 4 1:1 16MB windows, so the RAM should not be more than
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* 64 MB for this to work. If your memory is anywhere else
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* than at 0x0 you need to alter this.
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*/
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dma-ranges =
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<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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/* Each unique DTS using PCI must specify the swizzling */
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};
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uart0: serial@c8000000 {
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compatible = "intel,xscale-uart";
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reg = <0xc8000000 0x1000>;
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@ -61,9 +110,42 @@
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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};
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npe@c8006000 {
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npe: npe@c8006000 {
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compatible = "intel,ixp4xx-network-processing-engine";
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reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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};
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/* This is known as EthB */
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ethernet@c8009000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc8009000 0x1000>;
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status = "disabled";
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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intel,npe-handle = <&npe 1>;
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};
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/* This is known as EthC */
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ethernet@c800a000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc800a000 0x1000>;
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status = "disabled";
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 0>;
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queue-txready = <&qmgr 0>;
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intel,npe-handle = <&npe 2>;
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};
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/* This is known as EthA */
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ethernet@c800c000 {
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compatible = "intel,ixp4xx-ethernet";
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reg = <0xc800c000 0x1000>;
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status = "disabled";
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intel,npe = <0>;
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/* Dummy values that depend on firmware */
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queue-rx = <&qmgr 0>;
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queue-txready = <&qmgr 0>;
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};
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};
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};
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Loading…
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Block a user