forked from Minki/linux
clk: imx8mn: add clkout1/2 support
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
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"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
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"video_pll1_out", "osc_32k", };
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static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
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"dummy", "dummy", "gpu_pll_out", "dummy",
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"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
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"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
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static struct clk_hw_onecell_data *clk_hw_data;
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static struct clk_hw **hws;
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@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
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hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
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hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
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hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
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hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
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hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
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hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
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hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
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np = dev->of_node;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (WARN_ON(IS_ERR(base))) {
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@ -234,6 +234,13 @@
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#define IMX8MN_CLK_A53_CORE 214
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#define IMX8MN_CLK_END 215
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#define IMX8MN_CLK_CLKOUT1_SEL 215
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#define IMX8MN_CLK_CLKOUT1_DIV 216
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#define IMX8MN_CLK_CLKOUT1 217
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#define IMX8MN_CLK_CLKOUT2_SEL 218
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#define IMX8MN_CLK_CLKOUT2_DIV 219
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#define IMX8MN_CLK_CLKOUT2 220
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#define IMX8MN_CLK_END 221
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#endif
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