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media: cedrus: Properly signal size in mode register

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Mode register also holds information if video width is bigger than 2048
and if it is equal to 4096.

Rework cedrus_engine_enable() to properly signal this properties.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Jernej Skrabec 2019-11-10 07:30:01 +01:00 committed by Mauro Carvalho Chehab
parent df4a3e7f88
commit 3aef46bd5b
6 changed files with 13 additions and 6 deletions
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2
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
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@ -485,7 +485,7 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx,
{ {
struct cedrus_dev *dev = ctx->dev; struct cedrus_dev *dev = ctx->dev;
cedrus_engine_enable(dev, CEDRUS_CODEC_H264); cedrus_engine_enable(ctx, CEDRUS_CODEC_H264);
cedrus_write(dev, VE_H264_SDROT_CTRL, 0); cedrus_write(dev, VE_H264_SDROT_CTRL, 0);
cedrus_write(dev, VE_H264_EXTRA_BUFFER1, cedrus_write(dev, VE_H264_EXTRA_BUFFER1,

2
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@ -276,7 +276,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
} }
/* Activate H265 engine. */ /* Activate H265 engine. */
cedrus_engine_enable(dev, CEDRUS_CODEC_H265); cedrus_engine_enable(ctx, CEDRUS_CODEC_H265);
/* Source offset and length in bits. */ /* Source offset and length in bits. */

9
drivers/staging/media/sunxi/cedrus/cedrus_hw.c
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@ -30,7 +30,7 @@
#include "cedrus_hw.h" #include "cedrus_hw.h"
#include "cedrus_regs.h" #include "cedrus_regs.h"
int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec)
{ {
u32 reg = 0; u32 reg = 0;
@ -58,7 +58,12 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec)
return -EINVAL; return -EINVAL;
} }
cedrus_write(dev, VE_MODE, reg); if (ctx->src_fmt.width == 4096)
reg |= VE_MODE_PIC_WIDTH_IS_4096;
if (ctx->src_fmt.width > 2048)
reg |= VE_MODE_PIC_WIDTH_MORE_2048;
cedrus_write(ctx->dev, VE_MODE, reg);
return 0; return 0;
} }

2
drivers/staging/media/sunxi/cedrus/cedrus_hw.h
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@ -16,7 +16,7 @@
#ifndef _CEDRUS_HW_H_ #ifndef _CEDRUS_HW_H_
#define _CEDRUS_HW_H_ #define _CEDRUS_HW_H_
int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec);
void cedrus_engine_disable(struct cedrus_dev *dev); void cedrus_engine_disable(struct cedrus_dev *dev);
void cedrus_dst_format_set(struct cedrus_dev *dev, void cedrus_dst_format_set(struct cedrus_dev *dev,

2
drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c
View File

@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
quantization = run->mpeg2.quantization; quantization = run->mpeg2.quantization;
/* Activate MPEG engine. */ /* Activate MPEG engine. */
cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2); cedrus_engine_enable(ctx, CEDRUS_CODEC_MPEG2);
/* Set intra quantization matrix. */ /* Set intra quantization matrix. */

2
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
View File

@ -35,6 +35,8 @@
#define VE_MODE 0x00 #define VE_MODE 0x00
#define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
#define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
#define VE_MODE_REC_WR_MODE_2MB (0x01 << 20) #define VE_MODE_REC_WR_MODE_2MB (0x01 << 20)
#define VE_MODE_REC_WR_MODE_1MB (0x00 << 20) #define VE_MODE_REC_WR_MODE_1MB (0x00 << 20)
#define VE_MODE_DDR_MODE_BW_128 (0x03 << 16) #define VE_MODE_DDR_MODE_BW_128 (0x03 << 16)