dt-bindings: tegra: Convert Tegra PMC bindings to YAML
This patch converts text based Tegra PMC bindings document to YAML schema for performing dt validation. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sowjanya Komatineni
Thierry Reding
parent
e5377ab288
commit
39faeba707
@ -1,300 +0,0 @@
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NVIDIA Tegra Power Management Controller (PMC)
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== Power Management Controller Node ==
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain one of the following:
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For Tegra20 must contain "nvidia,tegra20-pmc".
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For Tegra30 must contain "nvidia,tegra30-pmc".
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For Tegra114 must contain "nvidia,tegra114-pmc"
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For Tegra124 must contain "nvidia,tegra124-pmc"
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For Tegra132 must contain "nvidia,tegra124-pmc"
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For Tegra210 must contain "nvidia,tegra210-pmc"
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Hardware-triggered thermal reset:
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On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
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hardware-triggered thermal reset will be enabled.
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Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
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described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
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Tegra K1 Technical Reference Manual.
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- nvidia,bus-addr : Bus address of the PMU on the I2C bus
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- nvidia,reg-addr : I2C register address to write poweroff command to
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- nvidia,reg-data : Poweroff command to write to PMU
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Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Optional nodes:
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- powergates : This node contains a hierarchy of power domain nodes, which
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should match the powergates on the Tegra SoC. See "Powergate
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Nodes" below.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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pmc@7000f400 {
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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== Powergate Nodes ==
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Each of the powergate nodes represents a power-domain on the Tegra SoC
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that can be power-gated by the Tegra PMC. The name of the powergate node
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should be one of the below. Note that not every powergate is applicable
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to all Tegra devices and the following list shows which powergates are
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applicable to which devices. Please refer to the Tegra TRM for more
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details on the various powergates.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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Required properties:
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- clocks: Must contain an entry for each clock required by the PMC for
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controlling a power-gate. See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each reset required by the PMC for
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controlling a power-gate. See ../reset/reset.txt for details.
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- #power-domain-cells: Must be 0.
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Example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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powergates {
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pd_audio: aud {
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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resets = <&tegra_car 198>;
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#power-domain-cells = <0>;
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};
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};
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};
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== Powergate Clients ==
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Hardware blocks belonging to a power domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding powergate node.
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Example:
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adma: adma@702e2000 {
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...
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power-domains = <&pd_audio>;
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...
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};
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== Pad Control ==
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On Tegra SoCs a pad is a set of pins which are configured as a group.
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The pin grouping is a fixed attribute of the hardware. The PMC can be
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used to set pad power state and signaling voltage. A pad can be either
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in active or power down mode. The support for power state and signaling
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voltage configuration varies depending on the pad in question. 3.3 V and
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1.8 V signaling voltages are supported on pins where software
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controllable signaling voltage switching is available.
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The pad configuration state nodes are placed under the pmc node and they
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are referred to by the pinctrl client properties. For more information
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see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
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The pad name should be used as the value of the pins property in pin
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configuration nodes.
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The following pads are present on Tegra124 and Tegra132:
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audio bb cam comp
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csia csb cse dsi
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dsib dsic dsid hdmi
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hsic hv lvds mipi-bias
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nand pex-bias pex-clk1 pex-clk2
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pex-cntrl sdmmc1 sdmmc3 sdmmc4
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sys_ddc uart usb0 usb1
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usb2 usb_bias
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The following pads are present on Tegra210:
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audio audio-hv cam csia
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csib csic csid csie
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csif dbg debug-nonao dmic
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dp dsi dsib dsic
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dsid emmc emmc2 gpio
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hdmi hsic lvds mipi-bias
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pex-bias pex-clk1 pex-clk2 pex-cntrl
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sdmmc1 sdmmc3 spi spi-hv
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uart usb0 usb1 usb2
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usb3 usb-bias
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Required pin configuration properties:
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- pins: Must contain name of the pad(s) to be configured.
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Optional pin configuration properties:
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- low-power-enable: Configure the pad into power down mode
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- low-power-disable: Configure the pad into active mode
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- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
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or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
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Note: The power state can be configured on all of the Tegra124 and
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Tegra132 pads. None of the Tegra124 or Tegra132 pads support
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signaling voltage switching.
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Note: All of the listed Tegra210 pads except pex-cntrl support power
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state configuration. Signaling voltage switching is supported on
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following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
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pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
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Pad configuration state example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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...
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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hdmi_off: hdmi-off {
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pins = "hdmi";
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low-power-enable;
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}
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hdmi_on: hdmi-on {
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pins = "hdmi";
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low-power-disable;
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}
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};
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Pinctrl client example:
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sdmmc1: sdhci@700b0000 {
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...
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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};
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...
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sor@54540000 {
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...
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pinctrl-0 = <&hdmi_off>;
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pinctrl-1 = <&hdmi_on>;
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pinctrl-names = "hdmi-on", "hdmi-off";
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};
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@ -0,0 +1,340 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Power Management Controller (PMC)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra20-pmc
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- nvidia,tegra20-pmc
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- nvidia,tegra30-pmc
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- nvidia,tegra114-pmc
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- nvidia,tegra124-pmc
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- nvidia,tegra210-pmc
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reg:
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maxItems: 1
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description:
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Offset and length of the register set for the device.
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clock-names:
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items:
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- const: pclk
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- const: clk32k_in
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description:
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Must includes entries pclk and clk32k_in.
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pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
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input to Tegra.
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clocks:
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maxItems: 2
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description:
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Must contain an entry for each entry in clock-names.
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See ../clocks/clocks-bindings.txt for details.
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'#interrupt-cells':
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const: 2
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description:
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Specifies number of cells needed to encode an interrupt source.
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The value must be 2.
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interrupt-controller: true
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nvidia,invert-interrupt:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and
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then fed into the ARM GIC. The PMC is not involved in the detection
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or handling of this interrupt signal, merely its inversion.
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nvidia,core-power-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Core power request active-high.
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nvidia,sys-clock-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: System clock request active-high.
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nvidia,combined-power-req:
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$ref: /schemas/types.yaml#/definitions/flag
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description: combined power request for CPU and Core.
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nvidia,cpu-pwr-good-en:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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CPU power good signal from external PMIC to PMC is enabled.
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nvidia,suspend-mode:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [0, 1, 2]
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description:
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The suspend mode that the platform should use.
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Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
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Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
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Mode 2 is for LP2, CPU voltage off
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nvidia,cpu-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power good time in uSec.
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nvidia,cpu-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power off time in uSec.
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nvidia,core-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<Oscillator-stable-time Power-stable-time>
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Core power good time in uSec.
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nvidia,core-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Core power off time in uSec.
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nvidia,lp0-vec:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<start length> Starting address and length of LP0 vector.
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The LP0 vector contains the warm boot code that is executed
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by AVP when resuming from the LP0 state.
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The AVP (Audio-Video Processor) is an ARM7 processor and
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always being the first boot processor when chip is power on
|
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or resume from deep sleep mode. When the system is resumed
|
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from the deep sleep mode, the warm boot code will restore
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some PLLs, clocks and then brings up CPU0 for resuming the
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system.
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i2c-thermtrip:
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type: object
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description:
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On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
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hardware-triggered thermal reset will be enabled.
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properties:
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nvidia,i2c-controller-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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ID of I2C controller to send poweroff command to PMU.
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Valid values are described in section 9.2.148
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"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
|
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Manual.
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nvidia,bus-addr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Bus address of the PMU on the I2C bus.
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||||
nvidia,reg-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: PMU I2C register address to issue poweroff command.
|
||||
|
||||
nvidia,reg-data:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Poweroff command to write to PMU.
|
||||
|
||||
nvidia,pinmux-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Pinmux used by the hardware when issuing Poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
required:
|
||||
- nvidia,i2c-controller-id
|
||||
- nvidia,bus-addr
|
||||
- nvidia,reg-addr
|
||||
- nvidia,reg-data
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
powergates:
|
||||
type: object
|
||||
description: |
|
||||
This node contains a hierarchy of power domain nodes, which should
|
||||
match the powergates on the Tegra SoC. Each powergate node
|
||||
represents a power-domain on the Tegra SoC that can be power-gated
|
||||
by the Tegra PMC.
|
||||
Hardware blocks belonging to a power domain should contain
|
||||
"power-domains" property that is a phandle pointing to corresponding
|
||||
powergate node.
|
||||
The name of the powergate node should be one of the below. Note that
|
||||
not every powergate is applicable to all Tegra devices and the following
|
||||
list shows which powergates are applicable to which devices.
|
||||
Please refer to Tegra TRM for mode details on the powergate nodes to
|
||||
use for each power-gate block inside Tegra.
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each clock required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../clocks/clock-bindings.txt document for more details.
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each reset required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^[a-f0-9]+-[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
This is a Pad configuration node. On Tegra SOCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power state
|
||||
and signaling voltage. A pad can be either in active or power down mode.
|
||||
The support for power state and signaling voltage configuration varies
|
||||
depending on the pad in question. 3.3V and 1.8V signaling voltages
|
||||
are supported on pins where software controllable signaling voltage
|
||||
switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132
|
||||
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
|
||||
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
|
||||
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
|
||||
|
||||
The following pads are present on Tegra210
|
||||
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
|
||||
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
|
||||
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain name of the pad(s) to be configured.
|
||||
|
||||
low-power-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into power down mode.
|
||||
|
||||
low-power-disable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into active mode.
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
Power state can be configured on all Tegra124 and Tegra132
|
||||
pads. None of the Tegra124 or Tegra132 pads support signaling
|
||||
voltage switching.
|
||||
All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported
|
||||
on below Tegra210 pads.
|
||||
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
dependencies:
|
||||
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
|
||||
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
|
||||
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user