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Merge remote-tracking branch 'kumar/next' into next

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Freescale updates from Kumar
This commit is contained in:
Benjamin Herrenschmidt 2012-11-26 09:25:25 +11:00
commit 3991782ea3
10 changed files with 250 additions and 20 deletions
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81
Documentation/devicetree/bindings/powerpc/fsl/raideng.txt Normal file
View File

@ -0,0 +1,81 @@
* Freescale 85xx RAID Engine nodes
RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
Engine should have a separate node.
Supported chips:
P5020, P5040
Required properties:
- compatible: Should contain "fsl,raideng-v1.0" as the value
This identifies RAID Engine block. 1 in 1.0 represents
major number whereas 0 represents minor number. The
version matches the hardware IP version.
- reg: offset and length of the register set for the device
- ranges: standard ranges property specifying the translation
between child address space and parent address space
Example:
/* P5020 */
raideng: raideng@320000 {
compatible = "fsl,raideng-v1.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x320000 0x10000>;
ranges = <0 0x320000 0x10000>;
};
There must be a sub-node for each job queue present in RAID Engine
This node must be a sub-node of the main RAID Engine node
- compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value
This identifies the job queue interface
- reg: offset and length of the register set for job queue
- ranges: standard ranges property specifying the translation
between child address space and parent address space
Example:
/* P5020 */
raideng_jq0@1000 {
compatible = "fsl,raideng-v1.0-job-queue";
reg = <0x1000 0x1000>;
ranges = <0x0 0x1000 0x1000>;
};
There must be a sub-node for each job ring present in RAID Engine
This node must be a sub-node of job queue node
- compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value
This identifies job ring. Should contain either
"fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring"
depending upon whether ring has high or low priority
- reg: offset and length of the register set for job ring
- interrupts: interrupt mapping for job ring IRQ
Optional property:
- fsl,liodn: Specifies the LIODN to be used for Job Ring. This
property is normally set by firmware. Value
is of 12-bits which is the LIODN number for this JR.
This property is used by the IOMMU (PAMU) to distinquish
transactions from this JR and than be able to do address
translation & protection accordingly.
Example:
/* P5020 */
raideng_jq0@1000 {
compatible = "fsl,raideng-v1.0-job-queue";
reg = <0x1000 0x1000>;
ranges = <0x0 0x1000 0x1000>;
raideng_jr0: jr@0 {
compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
reg = <0x0 0x400>;
interrupts = <139 2 0 0>;
interrupt-parent = <&mpic>;
fsl,liodn = <0x41>;
};
};

1
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
View File

@ -354,4 +354,5 @@
/include/ "qoriq-sata2-0.dtsi"
/include/ "qoriq-sata2-1.dtsi"
/include/ "qoriq-sec4.2-0.dtsi"
/include/ "qoriq-raid1.0-0.dtsi"
};

6
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
View File

@ -73,6 +73,12 @@
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
raideng = &raideng;
raideng_jr0 = &raideng_jr0;
raideng_jr1 = &raideng_jr1;
raideng_jr2 = &raideng_jr2;
raideng_jr3 = &raideng_jr3;
};
cpus {

85
arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi Normal file
View File

@ -0,0 +1,85 @@
/*
* QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ]
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
raideng: raideng@320000 {
compatible = "fsl,raideng-v1.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x320000 0x10000>;
ranges = <0 0x320000 0x10000>;
raideng_jq0@1000 {
compatible = "fsl,raideng-v1.0-job-queue";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1000 0x1000>;
ranges = <0x0 0x1000 0x1000>;
raideng_jr0: jr@0 {
compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
reg = <0x0 0x400>;
interrupts = <139 2 0 0>;
interrupt-parent = <&mpic>;
};
raideng_jr1: jr@400 {
compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
reg = <0x400 0x400>;
interrupts = <140 2 0 0>;
interrupt-parent = <&mpic>;
};
};
raideng_jq1@2000 {
compatible = "fsl,raideng-v1.0-job-queue";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2000 0x1000>;
ranges = <0x0 0x2000 0x1000>;
raideng_jr2: jr@0 {
compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
reg = <0x0 0x400>;
interrupts = <141 2 0 0>;
interrupt-parent = <&mpic>;
};
raideng_jr3: jr@400 {
compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
reg = <0x400 0x400>;
interrupts = <142 2 0 0>;
interrupt-parent = <&mpic>;
};
};
};

4
arch/powerpc/include/asm/fsl_guts.h
View File

@ -71,7 +71,9 @@ struct ccsr_guts {
u8 res0c4[0x224 - 0xc4];
__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
u8 res22c[0x800 - 0x22c];
u8 res22c[0x604 - 0x22c];
__be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
u8 res608[0x800 - 0x608];
__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
u8 res804[0x900 - 0x804];
__be32 ircr; /* 0x.0900 - Infrared Control Register */

2
arch/powerpc/platforms/85xx/p1022_ds.c
View File

@ -249,7 +249,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
goto exit;
}
iprop = of_get_property(law_node, "fsl,num-laws", 0);
iprop = of_get_property(law_node, "fsl,num-laws", NULL);
if (!iprop) {
pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
goto exit;

49
arch/powerpc/platforms/85xx/smp.c
View File

@ -128,6 +128,19 @@ static void __cpuinit smp_85xx_mach_cpu_die(void)
}
#endif
static inline void flush_spin_table(void *spin_table)
{
flush_dcache_range((ulong)spin_table,
(ulong)spin_table + sizeof(struct epapr_spin_table));
}
static inline u32 read_spin_table_addr_l(void *spin_table)
{
flush_dcache_range((ulong)spin_table,
(ulong)spin_table + sizeof(struct epapr_spin_table));
return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
}
static int __cpuinit smp_85xx_kick_cpu(int nr)
{
unsigned long flags;
@ -161,8 +174,8 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
/* Map the spin table */
if (ioremappable)
spin_table = ioremap(*cpu_rel_addr,
sizeof(struct epapr_spin_table));
spin_table = ioremap_prot(*cpu_rel_addr,
sizeof(struct epapr_spin_table), _PAGE_COHERENT);
else
spin_table = phys_to_virt(*cpu_rel_addr);
@ -173,7 +186,16 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
generic_set_cpu_up(nr);
if (system_state == SYSTEM_RUNNING) {
/*
* To keep it compatible with old boot program which uses
* cache-inhibit spin table, we need to flush the cache
* before accessing spin table to invalidate any staled data.
* We also need to flush the cache after writing to spin
* table to push data out.
*/
flush_spin_table(spin_table);
out_be32(&spin_table->addr_l, 0);
flush_spin_table(spin_table);
/*
* We don't set the BPTR register here since it already points
@ -181,9 +203,14 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
*/
mpic_reset_core(hw_cpu);
/* wait until core is ready... */
if (!spin_event_timeout(in_be32(&spin_table->addr_l) == 1,
10000, 100)) {
/*
* wait until core is ready...
* We need to invalidate the stale data, in case the boot
* loader uses a cache-inhibited spin table.
*/
if (!spin_event_timeout(
read_spin_table_addr_l(spin_table) == 1,
10000, 100)) {
pr_err("%s: timeout waiting for core %d to reset\n",
__func__, hw_cpu);
ret = -ENOENT;
@ -194,12 +221,10 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
__secondary_hold_acknowledge = -1;
}
#endif
flush_spin_table(spin_table);
out_be32(&spin_table->pir, hw_cpu);
out_be32(&spin_table->addr_l, __pa(__early_start));
if (!ioremappable)
flush_dcache_range((ulong)spin_table,
(ulong)spin_table + sizeof(struct epapr_spin_table));
flush_spin_table(spin_table);
/* Wait a bit for the CPU to ack. */
if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
@ -213,13 +238,11 @@ out:
#else
smp_generic_kick_cpu(nr);
flush_spin_table(spin_table);
out_be32(&spin_table->pir, hw_cpu);
out_be64((u64 *)(&spin_table->addr_h),
__pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
if (!ioremappable)
flush_dcache_range((ulong)spin_table,
(ulong)spin_table + sizeof(struct epapr_spin_table));
flush_spin_table(spin_table);
#endif
local_irq_restore(flags);

2
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
View File

@ -353,5 +353,7 @@ define_machine(mpc86xx_hpcd) {
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};

37
arch/powerpc/sysdev/fsl_pci.c
View File

@ -89,7 +89,7 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
return 0;
}
static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
unsigned int index, const struct resource *res,
resource_size_t offset)
{
@ -126,7 +126,7 @@ static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
static void __init setup_pci_atmu(struct pci_controller *hose,
static void setup_pci_atmu(struct pci_controller *hose,
struct resource *rsrc)
{
struct ccsr_pci __iomem *pci;
@ -902,9 +902,42 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static int fsl_pci_resume(struct device *dev)
{
struct pci_controller *hose;
struct resource pci_rsrc;
hose = pci_find_hose_for_OF_device(dev->of_node);
if (!hose)
return -ENODEV;
if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
dev_err(dev, "Get pci register base failed.");
return -ENODEV;
}
setup_pci_atmu(hose, &pci_rsrc);
return 0;
}
static const struct dev_pm_ops pci_pm_ops = {
.resume = fsl_pci_resume,
};
#define PCI_PM_OPS (&pci_pm_ops)
#else
#define PCI_PM_OPS NULL
#endif
static struct platform_driver fsl_pci_driver = {
.driver = {
.name = "fsl-pci",
.pm = PCI_PM_OPS,
.of_match_table = pci_ids,
},
.probe = fsl_pci_probe,

3
drivers/virt/fsl_hypervisor.c
View File

@ -796,9 +796,6 @@ static int has_fsl_hypervisor(void)
struct device_node *node;
int ret;
if (!(mfmsr() & MSR_GS))
return 0;
node = of_find_node_by_path("/hypervisor");
if (!node)
return 0;