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[ARM] 3825/1: iop3xx: use cp6 enable/disable macros

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Add CP6 enable/disable sequences to the timekeeping code and the IRQ
code.  As a result, we can't depend on CP6 access being enabled when
we enter get_irqnr_and_base anymore, so switch the latter over to
using memory-mapped accesses for now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek 2006-09-18 23:21:38 +01:00 committed by Russell King
parent 0b29de4a6a
commit 38ce73ebd7
5 changed files with 23 additions and 39 deletions
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23
arch/arm/mach-iop32x/irq.c
View File

@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */;
static inline void intctl_write(u32 val)
{
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write(u32 val)
{
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static void
@ -61,24 +65,7 @@ struct irq_chip ext_chip = {
void __init iop321_init_irq(void)
{
unsigned int i, tmp;
/* Enable access to coprocessor 6 for dealing with IRQs.
* From RMK:
* Basically, the Intel documentation here is poor. It appears that
* you need to set the bit to be able to access the coprocessor from
* SVC mode. Whether that allows access from user space or not is
* unclear.
*/
asm volatile (
"mrc p15, 0, %0, c15, c1, 0\n\t"
"orr %0, %0, %1\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
/* The action is delayed, so we have to do this: */
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4"
: "=r" (tmp) : "i" (1 << 6) );
unsigned int i;
intctl_write(0); // disable all interrupts
intstr_write(0); // treat all as IRQ

27
arch/arm/mach-iop33x/irq.c
View File

@ -28,25 +28,33 @@ static u32 iop331_mask1 = 0;
static inline void intctl_write0(u32 val)
{
// INTCTL0
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static inline void intctl_write1(u32 val)
{
// INTCTL1
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write0(u32 val)
{
// INTSTR0
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write1(u32 val)
{
// INTSTR1
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
iop3xx_cp6_disable();
}
static void
@ -93,24 +101,7 @@ struct irq_chip iop331_irqchip2 = {
void __init iop331_init_irq(void)
{
unsigned int i, tmp;
/* Enable access to coprocessor 6 for dealing with IRQs.
* From RMK:
* Basically, the Intel documentation here is poor. It appears that
* you need to set the bit to be able to access the coprocessor from
* SVC mode. Whether that allows access from user space or not is
* unclear.
*/
asm volatile (
"mrc p15, 0, %0, c15, c1, 0\n\t"
"orr %0, %0, %1\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
/* The action is delayed, so we have to do this: */
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4"
: "=r" (tmp) : "i" (1 << 6) );
unsigned int i;
intctl_write0(0); // disable all interrupts
intctl_write1(0);

4
arch/arm/plat-iop/time.c
View File

@ -51,7 +51,9 @@ iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
iop3xx_cp6_disable();
while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
>= ticks_per_jiffy) {
@ -85,10 +87,12 @@ void __init iop3xx_init_time(unsigned long tick_rate)
* We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies.
*/
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
iop3xx_cp6_disable();
setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
}

3
include/asm-arm/arch-iop32x/entry-macro.S
View File

@ -17,7 +17,8 @@
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
ldr \base, =IOP3XX_REG_ADDR(0x07D8)
ldr \irqstat, [\base] @ Read IINTSRC
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat

5
include/asm-arm/arch-iop33x/entry-macro.S
View File

@ -17,10 +17,11 @@
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
ldr \base, =IOP3XX_REG_ADDR(0x7A0)
ldr \irqstat, [\base] @ Read IINTSRC0
cmp \irqstat, #0
bne 1002f
mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
ldr \irqstat, [\base, #4] @ Read IINTSRC1
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat