forked from Minki/linux
MIPS: Netlogic: PIC IRQ handling update for multi-chip
Create struct nlm_pic_irq for interrupts handled by the PIC. This simplifies IRQ handling for multi-SoC as well as the single SoC cases. Also split the setup of percpu and PIC interrupts so that we can configure the PIC interrupts for every node. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4467 Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
John Crispin
parent
bb1e4bc5cd
commit
38541742da
@ -53,7 +53,7 @@
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struct irq_desc;
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_irq_init(void);
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void nlm_smp_irq_init(int hwcpuid);
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void nlm_boot_secondary_cpus(void);
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int nlm_wakeup_secondary_cpus(void);
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void nlm_rmiboot_preboot(void);
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@ -382,7 +382,6 @@ nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
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}
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int nlm_irq_to_irt(int irq);
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int nlm_irt_to_irq(int irt);
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#endif /* __ASSEMBLY__ */
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#endif /* _NLM_HAL_PIC_H */
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@ -36,7 +36,6 @@
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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@ -62,68 +61,66 @@
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#else
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#error "Unknown CPU"
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#endif
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/*
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* These are the routines that handle all the low level interrupt stuff.
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* Actions handled here are: initialization of the interrupt map, requesting of
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* interrupt lines by handlers, dispatching if interrupts to handlers, probing
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* for interrupt lines
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*/
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/* Globals */
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#ifdef CONFIG_SMP
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#define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \
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(1ULL << IRQ_IPI_SMP_RESCHEDULE))
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#else
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#define SMP_IRQ_MASK 0
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#endif
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#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER))
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struct nlm_pic_irq {
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void (*extra_ack)(struct irq_data *);
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struct nlm_soc_info *node;
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int picirq;
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int irt;
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int flags;
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};
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static void xlp_pic_enable(struct irq_data *d)
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{
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unsigned long flags;
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struct nlm_soc_info *nodep;
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int irt;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_enable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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BUG_ON(!pd);
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spin_lock_irqsave(&pd->node->piclock, flags);
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nlm_pic_enable_irt(pd->node->picbase, pd->irt);
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spin_unlock_irqrestore(&pd->node->piclock, flags);
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}
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static void xlp_pic_disable(struct irq_data *d)
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{
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struct nlm_soc_info *nodep;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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unsigned long flags;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_disable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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BUG_ON(!pd);
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spin_lock_irqsave(&pd->node->piclock, flags);
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nlm_pic_disable_irt(pd->node->picbase, pd->irt);
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spin_unlock_irqrestore(&pd->node->piclock, flags);
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}
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static void xlp_pic_mask_ack(struct irq_data *d)
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{
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uint64_t mask = 1ull << d->irq;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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uint64_t mask = 1ull << pd->picirq;
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write_c0_eirr(mask); /* ack by writing EIRR */
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}
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static void xlp_pic_unmask(struct irq_data *d)
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{
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void *hd = irq_data_get_irq_handler_data(d);
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struct nlm_soc_info *nodep;
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int irt;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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if (!pd)
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return;
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if (hd) {
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void (*extra_ack)(void *) = hd;
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extra_ack(d);
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}
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if (pd->extra_ack)
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pd->extra_ack(d);
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/* Ack is a single write, no need to lock */
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nlm_pic_ack(nodep->picbase, irt);
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nlm_pic_ack(pd->node->picbase, pd->irt);
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}
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static struct irq_chip xlp_pic = {
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@ -177,51 +174,84 @@ struct irq_chip nlm_cpu_intr = {
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.irq_eoi = cpuintr_ack,
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};
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void __init init_nlm_common_irqs(void)
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static void __init nlm_init_percpu_irqs(void)
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{
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int i, irq, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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int i;
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nodep = nlm_current_node();
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irqmask = (1ULL << IRQ_TIMER);
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for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
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irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
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for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
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irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
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#ifdef CONFIG_SMP
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irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
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nlm_smp_function_ipi_handler);
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irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
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nlm_smp_resched_ipi_handler);
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irqmask |=
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((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
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#endif
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}
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for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
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irt = nlm_irq_to_irt(irq);
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void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
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{
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struct nlm_pic_irq *pic_data;
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int xirq;
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xirq = nlm_irq_to_xirq(node, irq);
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pic_data = kzalloc(sizeof(*pic_data), GFP_KERNEL);
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BUG_ON(pic_data == NULL);
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pic_data->irt = irt;
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pic_data->picirq = picirq;
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pic_data->node = nlm_get_node(node);
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irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
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irq_set_handler_data(xirq, pic_data);
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}
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void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
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{
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struct nlm_pic_irq *pic_data;
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int xirq;
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xirq = nlm_irq_to_xirq(node, irq);
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pic_data = irq_get_handler_data(xirq);
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pic_data->extra_ack = xack;
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}
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static void nlm_init_node_irqs(int node)
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{
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int i, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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pr_info("Init IRQ for node %d\n", node);
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nodep = nlm_get_node(node);
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irqmask = PERCPU_IRQ_MASK;
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for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
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irt = nlm_irq_to_irt(i);
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if (irt == -1)
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continue;
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irqmask |= (1ULL << irq);
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nlm_pic_init_irt(nodep->picbase, irt, irq, 0);
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nlm_setup_pic_irq(node, i, i, irt);
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/* set interrupts to first cpu in node */
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nlm_pic_init_irt(nodep->picbase, irt, i,
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node * NLM_CPUS_PER_NODE);
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irqmask |= (1ull << i);
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}
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nodep->irqmask = irqmask;
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}
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void __init arch_init_irq(void)
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{
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/* Initialize the irq descriptors */
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init_nlm_common_irqs();
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nlm_init_percpu_irqs();
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nlm_init_node_irqs(0);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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void __cpuinit nlm_smp_irq_init(void)
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void nlm_smp_irq_init(int hwcpuid)
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{
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/* set interrupt mask for non-zero cpus */
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int node, cpu;
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node = hwcpuid / NLM_CPUS_PER_NODE;
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cpu = hwcpuid % NLM_CPUS_PER_NODE;
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if (cpu == 0 && node != 0)
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nlm_init_node_irqs(node);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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@ -232,23 +262,17 @@ asmlinkage void plat_irq_dispatch(void)
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node = nlm_nodeid();
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eirr = read_c0_eirr() & read_c0_eimr();
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if (eirr & (1 << IRQ_TIMER)) {
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do_IRQ(IRQ_TIMER);
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return;
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}
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#ifdef CONFIG_SMP
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if (eirr & IRQ_IPI_SMP_FUNCTION) {
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do_IRQ(IRQ_IPI_SMP_FUNCTION);
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return;
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}
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if (eirr & IRQ_IPI_SMP_RESCHEDULE) {
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do_IRQ(IRQ_IPI_SMP_RESCHEDULE);
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return;
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}
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#endif
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i = __ilog2_u64(eirr);
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if (i == -1)
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return;
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/* per-CPU IRQs don't need translation */
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if (eirr & PERCPU_IRQ_MASK) {
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do_IRQ(i);
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return;
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}
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/* top level irq handling */
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do_IRQ(nlm_irq_to_xirq(node, i));
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}
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@ -114,8 +114,11 @@ void nlm_early_init_secondary(int cpu)
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*/
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static void __cpuinit nlm_init_secondary(void)
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{
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current_cpu_data.core = hard_smp_processor_id() / NLM_THREADS_PER_CORE;
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nlm_smp_irq_init();
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int hwtid;
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hwtid = hard_smp_processor_id();
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current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
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nlm_smp_irq_init(hwtid);
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}
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void nlm_prepare_cpus(unsigned int max_cpus)
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@ -100,44 +100,6 @@ int nlm_irq_to_irt(int irq)
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}
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}
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int nlm_irt_to_irq(int irt)
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{
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switch (irt) {
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case PIC_IRT_UART_0_INDEX:
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return PIC_UART_0_IRQ;
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case PIC_IRT_UART_1_INDEX:
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return PIC_UART_1_IRQ;
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case PIC_IRT_PCIE_LINK_0_INDEX:
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return PIC_PCIE_LINK_0_IRQ;
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case PIC_IRT_PCIE_LINK_1_INDEX:
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return PIC_PCIE_LINK_1_IRQ;
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case PIC_IRT_PCIE_LINK_2_INDEX:
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return PIC_PCIE_LINK_2_IRQ;
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case PIC_IRT_PCIE_LINK_3_INDEX:
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return PIC_PCIE_LINK_3_IRQ;
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case PIC_IRT_EHCI_0_INDEX:
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return PIC_EHCI_0_IRQ;
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case PIC_IRT_EHCI_1_INDEX:
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return PIC_EHCI_1_IRQ;
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case PIC_IRT_OHCI_0_INDEX:
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return PIC_OHCI_0_IRQ;
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case PIC_IRT_OHCI_1_INDEX:
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return PIC_OHCI_1_IRQ;
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case PIC_IRT_OHCI_2_INDEX:
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return PIC_OHCI_2_IRQ;
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case PIC_IRT_OHCI_3_INDEX:
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return PIC_OHCI_3_IRQ;
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case PIC_IRT_MMC_INDEX:
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return PIC_MMC_IRQ;
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case PIC_IRT_I2C_0_INDEX:
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return PIC_I2C_0_IRQ;
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case PIC_IRT_I2C_1_INDEX:
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return PIC_I2C_1_IRQ;
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default:
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return -1;
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}
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}
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unsigned int nlm_get_core_frequency(int node, int core)
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{
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unsigned int pll_divf, pll_divr, dfs_div, ext_div;
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