forked from Minki/linux
drm/i915: Don't fiddle with rps/rc6 across GPU reset
Resetting the GPU doesn't affect the RPS/RC6 state, so we can stop forcibly reloading the registers. Ville suggested this many moons ago, I said at that time that sanitizing was no harm and meant that our bookkeeping was kept consistent with the HW. However, in a forthcoming series, we want to split rps/rc6 GT powermanagement and one of the key simplifications is the control of when we enable it. Performing a crude sanitize in the middle of i915_gem_reset() is then a huge wart. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180410133354.13425-1-chris@chris-wilson.co.uk
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@ -3254,13 +3254,6 @@ void i915_gem_reset(struct drm_i915_private *dev_priv,
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}
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i915_gem_restore_fences(dev_priv);
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if (dev_priv->gt.awake) {
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intel_sanitize_gt_powersave(dev_priv);
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intel_enable_gt_powersave(dev_priv);
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if (INTEL_GEN(dev_priv) >= 6)
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gen6_rps_busy(dev_priv);
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}
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}
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void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
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