diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 29663db5afcd..900e07bb54ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1799,9 +1799,8 @@ dp_to_i915(struct intel_dp *intel_dp)
 	return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 }
 
-#define CAN_PSR(intel_dp)	(HAS_PSR(dp_to_i915(intel_dp)) && \
-				 (intel_dp)->psr.sink_support && \
-				 (intel_dp)->psr.source_support)
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
+			   (intel_dp)->psr.source_support)
 
 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f89e0de5dde..0a0cc61344c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2358,7 +2358,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
 		return false;
 	}
 
-	if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
+	if (CAN_PSR(intel_dp)) {
 		drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
 		crtc_state->uapi.mode_changed = true;
 		return false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7ce4feaf18a1..581d2e83bbee 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1964,7 +1964,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
 			  DP_PSR_LINK_CRC_ERROR;
 
-	if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
+	if (!CAN_PSR(intel_dp))
 		return;
 
 	mutex_lock(&psr->lock);
@@ -2014,7 +2014,7 @@ bool intel_psr_enabled(struct intel_dp *intel_dp)
 {
 	bool ret;
 
-	if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
+	if (!CAN_PSR(intel_dp))
 		return false;
 
 	mutex_lock(&intel_dp->psr.lock);