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powerpc/fsl-booke: Handle L1 D-cache parity error correctly on e500mc

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If the L1 D-Cache is in write shadow mode the HW will auto-recover the
error.  However we might still log the error and cause a machine check
(if L1CSR0[CPE] - Cache error checking enable).  We should only treat
the non-write shadow case as non-recoverable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-08-27 06:14:23 -05:00
parent 09af52f78e
commit 37caf9f2a1
2 changed files with 11 additions and 1 deletions
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3
arch/powerpc/include/asm/reg_booke.h
View File

@ -548,6 +548,9 @@
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
/* Bit definitions for L1CSR2. */
#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
/* Bit definitions for L2CSR0. */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */

9
arch/powerpc/kernel/traps.c
View File

@ -457,7 +457,14 @@ int machine_check_e500mc(struct pt_regs *regs)
if (reason & MCSR_DCPERR_MC) {
printk("Data Cache Parity Error\n");
recoverable = 0;
/*
* In write shadow mode we auto-recover from the error, but it
* may still get logged and cause a machine check. We should
* only treat the non-write shadow case as non-recoverable.
*/
if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
recoverable = 0;
}
if (reason & MCSR_L2MMU_MHIT) {