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ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

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Because of commit 9cb2ff1117 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb83 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
This commit is contained in:
Dinh Nguyen 2021-11-22 09:10:03 -06:00
parent f34e8875ae
commit 36de991e93
4 changed files with 4 additions and 4 deletions
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2
arch/arm/boot/dts/socfpga.dtsi
View File

@ -782,7 +782,7 @@
};
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,

2
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -756,7 +756,7 @@
};
qspi: spi@ff809000 {
compatible = "cdns,qspi-nor";
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff809000 0x100>,

2
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -594,7 +594,7 @@
};
qspi: spi@ff8d2000 {
compatible = "cdns,qspi-nor";
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,

2
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -628,7 +628,7 @@
};
qspi: spi@ff8d2000 {
compatible = "cdns,qspi-nor";
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,