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Merge master.kernel.org:/home/rmk/linux-2.6-serial

Browse Source 
* master.kernel.org:/home/rmk/linux-2.6-serial:
  [ARM] 3383/3: ixp2000: ixdp2x01 platform serial conversion
  [SERIAL] amba-pl010: Remove accessor macros
  [SERIAL] remove 8250_acpi (replaced by 8250_pnp and PNPACPI)
  [SERIAL] icom: select FW_LOADER
This commit is contained in:
Linus Torvalds 2006-03-25 20:31:32 -08:00
commit 36ddf5bbde
6 changed files with 122 additions and 284 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
arch/arm/mach-ixp2000/ixdp2x01.c
View File

@ -30,6 +30,7 @@
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/io.h>
#include <asm/irq.h>
@ -132,7 +133,7 @@ void __init ixdp2x01_init_irq(void)
/*************************************************************************
* IXDP2x01 memory map and serial ports
* IXDP2x01 memory map
*************************************************************************/
static struct map_desc ixdp2x01_io_desc __initdata = {
.virtual = IXDP2X01_VIRT_CPLD_BASE,
@ -141,40 +142,78 @@ static struct map_desc ixdp2x01_io_desc __initdata = {
.type = MT_DEVICE
};
static struct uart_port ixdp2x01_serial_ports[2] = {
{
.membase = (char *)(IXDP2X01_UART1_VIRT_BASE),
.mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
.irq = IRQ_IXDP2X01_UART1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = IXDP2X01_UART_CLK,
.line = 1,
.type = PORT_16550A,
.fifosize = 16
}, {
.membase = (char *)(IXDP2X01_UART2_VIRT_BASE),
.mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
.irq = IRQ_IXDP2X01_UART2,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = IXDP2X01_UART_CLK,
.line = 2,
.type = PORT_16550A,
.fifosize = 16
},
};
static void __init ixdp2x01_map_io(void)
{
ixp2000_map_io();
iotable_init(&ixdp2x01_io_desc, 1);
}
early_serial_setup(&ixdp2x01_serial_ports[0]);
early_serial_setup(&ixdp2x01_serial_ports[1]);
/*************************************************************************
* IXDP2x01 serial ports
*************************************************************************/
static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
{
.mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
.membase = (char *)IXDP2X01_UART1_VIRT_BASE,
.irq = IRQ_IXDP2X01_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = IXDP2X01_UART_CLK,
},
{ }
};
static struct resource ixdp2x01_uart_resource1 = {
.start = IXDP2X01_UART1_PHYS_BASE,
.end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device ixdp2x01_serial_device1 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = ixdp2x01_serial_port1,
},
.num_resources = 1,
.resource = &ixdp2x01_uart_resource1,
};
static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
{
.mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
.membase = (char *)IXDP2X01_UART2_VIRT_BASE,
.irq = IRQ_IXDP2X01_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM32,
.regshift = 2,
.uartclk = IXDP2X01_UART_CLK,
},
{ }
};
static struct resource ixdp2x01_uart_resource2 = {
.start = IXDP2X01_UART2_PHYS_BASE,
.end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device ixdp2x01_serial_device2 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
.dev = {
.platform_data = ixdp2x01_serial_port2,
},
.num_resources = 1,
.resource = &ixdp2x01_uart_resource2,
};
static void ixdp2x01_uart_init(void)
{
platform_device_register(&ixdp2x01_serial_device1);
platform_device_register(&ixdp2x01_serial_device2);
}
@ -374,6 +413,7 @@ static void __init ixdp2x01_init_machine(void)
platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
ixp2000_uart_init();
ixdp2x01_uart_init();
}

183
drivers/serial/8250_acpi.c
View File

@ -1,183 +0,0 @@
/*
* Copyright (c) 2002-2003 Matthew Wilcox for Hewlett-Packard
* Copyright (C) 2004 Hewlett-Packard Co
* Bjorn Helgaas <bjorn.helgaas@hp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/serial_core.h>
#include <acpi/acpi_bus.h>
#include <asm/io.h>
#include "8250.h"
struct serial_private {
int line;
};
static acpi_status acpi_serial_mmio(struct uart_port *port,
struct acpi_resource_address64 *addr)
{
port->mapbase = addr->minimum;
port->iotype = UPIO_MEM;
port->flags |= UPF_IOREMAP;
return AE_OK;
}
static acpi_status acpi_serial_port(struct uart_port *port,
struct acpi_resource_io *io)
{
if (io->address_length) {
port->iobase = io->minimum;
port->iotype = UPIO_PORT;
} else
printk(KERN_ERR "%s: zero-length IO port range?\n", __FUNCTION__);
return AE_OK;
}
static acpi_status acpi_serial_ext_irq(struct uart_port *port,
struct acpi_resource_extended_irq *ext_irq)
{
int rc;
if (ext_irq->interrupt_count > 0) {
rc = acpi_register_gsi(ext_irq->interrupts[0],
ext_irq->triggering, ext_irq->polarity);
if (rc < 0)
return AE_ERROR;
port->irq = rc;
}
return AE_OK;
}
static acpi_status acpi_serial_irq(struct uart_port *port,
struct acpi_resource_irq *irq)
{
int rc;
if (irq->interrupt_count > 0) {
rc = acpi_register_gsi(irq->interrupts[0],
irq->triggering, irq->polarity);
if (rc < 0)
return AE_ERROR;
port->irq = rc;
}
return AE_OK;
}
static acpi_status acpi_serial_resource(struct acpi_resource *res, void *data)
{
struct uart_port *port = (struct uart_port *) data;
struct acpi_resource_address64 addr;
acpi_status status;
status = acpi_resource_to_address64(res, &addr);
if (ACPI_SUCCESS(status))
return acpi_serial_mmio(port, &addr);
else if (res->type == ACPI_RESOURCE_TYPE_IO)
return acpi_serial_port(port, &res->data.io);
else if (res->type == ACPI_RESOURCE_TYPE_EXTENDED_IRQ)
return acpi_serial_ext_irq(port, &res->data.extended_irq);
else if (res->type == ACPI_RESOURCE_TYPE_IRQ)
return acpi_serial_irq(port, &res->data.irq);
return AE_OK;
}
static int acpi_serial_add(struct acpi_device *device)
{
struct serial_private *priv;
acpi_status status;
struct uart_port port;
int result;
memset(&port, 0, sizeof(struct uart_port));
port.uartclk = 1843200;
port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
priv = kmalloc(sizeof(struct serial_private), GFP_KERNEL);
if (!priv) {
result = -ENOMEM;
goto fail;
}
memset(priv, 0, sizeof(*priv));
status = acpi_walk_resources(device->handle, METHOD_NAME__CRS,
acpi_serial_resource, &port);
if (ACPI_FAILURE(status)) {
result = -ENODEV;
goto fail;
}
if (!port.mapbase && !port.iobase) {
printk(KERN_ERR "%s: no iomem or port address in %s _CRS\n",
__FUNCTION__, device->pnp.bus_id);
result = -ENODEV;
goto fail;
}
priv->line = serial8250_register_port(&port);
if (priv->line < 0) {
printk(KERN_WARNING "Couldn't register serial port %s: %d\n",
device->pnp.bus_id, priv->line);
result = -ENODEV;
goto fail;
}
acpi_driver_data(device) = priv;
return 0;
fail:
kfree(priv);
return result;
}
static int acpi_serial_remove(struct acpi_device *device, int type)
{
struct serial_private *priv;
if (!device || !acpi_driver_data(device))
return -EINVAL;
priv = acpi_driver_data(device);
serial8250_unregister_port(priv->line);
kfree(priv);
return 0;
}
static struct acpi_driver acpi_serial_driver = {
.name = "serial",
.class = "",
.ids = "PNP0501",
.ops = {
.add = acpi_serial_add,
.remove = acpi_serial_remove,
},
};
static int __init acpi_serial_init(void)
{
return acpi_bus_register_driver(&acpi_serial_driver);
}
static void __exit acpi_serial_exit(void)
{
acpi_bus_unregister_driver(&acpi_serial_driver);
}
module_init(acpi_serial_init);
module_exit(acpi_serial_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Generic 8250/16x50 ACPI serial driver");

9
drivers/serial/Kconfig
View File

@ -77,14 +77,6 @@ config SERIAL_8250_CS
If unsure, say N.
config SERIAL_8250_ACPI
bool "8250/16550 device discovery via ACPI namespace"
default y if IA64
depends on ACPI && SERIAL_8250
---help---
If you wish to enable serial port discovery via the ACPI
namespace, say Y here. If unsure, say N.
config SERIAL_8250_NR_UARTS
int "Maximum number of 8250/16550 serial ports"
depends on SERIAL_8250
@ -827,6 +819,7 @@ config SERIAL_ICOM
tristate "IBM Multiport Serial Adapter"
depends on PCI && (PPC_ISERIES || PPC_PSERIES)
select SERIAL_CORE
select FW_LOADER
help
This driver is for a family of multiport serial adapters
including 2 port RVX, 2 port internal modem, 4 port internal

1
drivers/serial/Makefile
View File

@ -5,7 +5,6 @@
#
serial-8250-y :=
serial-8250-$(CONFIG_SERIAL_8250_ACPI) += 8250_acpi.o
serial-8250-$(CONFIG_PNP) += 8250_pnp.o
serial-8250-$(CONFIG_GSC) += 8250_gsc.o
serial-8250-$(CONFIG_PCI) += 8250_pci.o

110
drivers/serial/amba-pl010.c
View File

@ -62,26 +62,8 @@
#define AMBA_ISR_PASS_LIMIT 256
/*
* Access macros for the AMBA UARTs
*/
#define UART_GET_INT_STATUS(p) readb((p)->membase + UART010_IIR)
#define UART_PUT_ICR(p, c) writel((c), (p)->membase + UART010_ICR)
#define UART_GET_FR(p) readb((p)->membase + UART01x_FR)
#define UART_GET_CHAR(p) readb((p)->membase + UART01x_DR)
#define UART_PUT_CHAR(p, c) writel((c), (p)->membase + UART01x_DR)
#define UART_GET_RSR(p) readb((p)->membase + UART01x_RSR)
#define UART_GET_CR(p) readb((p)->membase + UART010_CR)
#define UART_PUT_CR(p,c) writel((c), (p)->membase + UART010_CR)
#define UART_GET_LCRL(p) readb((p)->membase + UART010_LCRL)
#define UART_PUT_LCRL(p,c) writel((c), (p)->membase + UART010_LCRL)
#define UART_GET_LCRM(p) readb((p)->membase + UART010_LCRM)
#define UART_PUT_LCRM(p,c) writel((c), (p)->membase + UART010_LCRM)
#define UART_GET_LCRH(p) readb((p)->membase + UART010_LCRH)
#define UART_PUT_LCRH(p,c) writel((c), (p)->membase + UART010_LCRH)
#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART01x_FR_TMSK) == 0)
#define UART_DUMMY_RSR_RX /*256*/0
#define UART_PORT_SIZE 64
@ -110,36 +92,36 @@ static void pl010_stop_tx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CR(port);
cr = readb(port->membase + UART010_CR);
cr &= ~UART010_CR_TIE;
UART_PUT_CR(port, cr);
writel(cr, port->membase + UART010_CR);
}
static void pl010_start_tx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CR(port);
cr = readb(port->membase + UART010_CR);
cr |= UART010_CR_TIE;
UART_PUT_CR(port, cr);
writel(cr, port->membase + UART010_CR);
}
static void pl010_stop_rx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CR(port);
cr = readb(port->membase + UART010_CR);
cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
UART_PUT_CR(port, cr);
writel(cr, port->membase + UART010_CR);
}
static void pl010_enable_ms(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CR(port);
cr = readb(port->membase + UART010_CR);
cr |= UART010_CR_MSIE;
UART_PUT_CR(port, cr);
writel(cr, port->membase + UART010_CR);
}
static void
@ -152,9 +134,9 @@ pl010_rx_chars(struct uart_port *port)
struct tty_struct *tty = port->info->tty;
unsigned int status, ch, flag, rsr, max_count = 256;
status = UART_GET_FR(port);
status = readb(port->membase + UART01x_FR);
while (UART_RX_DATA(status) && max_count--) {
ch = UART_GET_CHAR(port);
ch = readb(port->membase + UART01x_DR);
flag = TTY_NORMAL;
port->icount.rx++;
@ -163,7 +145,7 @@ pl010_rx_chars(struct uart_port *port)
* Note that the error handling code is
* out of the main execution path
*/
rsr = UART_GET_RSR(port) | UART_DUMMY_RSR_RX;
rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
if (unlikely(rsr & UART01x_RSR_ANY)) {
if (rsr & UART01x_RSR_BE) {
rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
@ -193,7 +175,7 @@ pl010_rx_chars(struct uart_port *port)
uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
ignore_char:
status = UART_GET_FR(port);
status = readb(port->membase + UART01x_FR);
}
tty_flip_buffer_push(tty);
return;
@ -205,7 +187,7 @@ static void pl010_tx_chars(struct uart_port *port)
int count;
if (port->x_char) {
UART_PUT_CHAR(port, port->x_char);
writel(port->x_char, port->membase + UART01x_DR);
port->icount.tx++;
port->x_char = 0;
return;
@ -217,7 +199,7 @@ static void pl010_tx_chars(struct uart_port *port)
count = port->fifosize >> 1;
do {
UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
if (uart_circ_empty(xmit))
@ -236,9 +218,9 @@ static void pl010_modem_status(struct uart_port *port)
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int status, delta;
UART_PUT_ICR(&uap->port, 0);
writel(0, uap->port.membase + UART010_ICR);
status = UART_GET_FR(&uap->port) & UART01x_FR_MODEM_ANY;
status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
delta = status ^ uap->old_status;
uap->old_status = status;
@ -266,7 +248,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
spin_lock(&port->lock);
status = UART_GET_INT_STATUS(port);
status = readb(port->membase + UART010_IIR);
if (status) {
do {
if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
@ -283,7 +265,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
if (pass_counter-- == 0)
break;
status = UART_GET_INT_STATUS(port);
status = readb(port->membase + UART010_IIR);
} while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
UART010_IIR_TIS));
handled = 1;
@ -296,7 +278,7 @@ static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
static unsigned int pl010_tx_empty(struct uart_port *port)
{
return UART_GET_FR(port) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
}
static unsigned int pl010_get_mctrl(struct uart_port *port)
@ -304,7 +286,7 @@ static unsigned int pl010_get_mctrl(struct uart_port *port)
unsigned int result = 0;
unsigned int status;
status = UART_GET_FR(port);
status = readb(port->membase + UART01x_FR);
if (status & UART01x_FR_DCD)
result |= TIOCM_CAR;
if (status & UART01x_FR_DSR)
@ -340,12 +322,12 @@ static void pl010_break_ctl(struct uart_port *port, int break_state)
unsigned int lcr_h;
spin_lock_irqsave(&port->lock, flags);
lcr_h = UART_GET_LCRH(port);
lcr_h = readb(port->membase + UART010_LCRH);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
UART_PUT_LCRH(port, lcr_h);
writel(lcr_h, port->membase + UART010_LCRH);
spin_unlock_irqrestore(&port->lock, flags);
}
@ -364,13 +346,13 @@ static int pl010_startup(struct uart_port *port)
/*
* initialise the old status of the modem signals
*/
uap->old_status = UART_GET_FR(port) & UART01x_FR_MODEM_ANY;
uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
/*
* Finally, enable interrupts
*/
UART_PUT_CR(port, UART01x_CR_UARTEN | UART010_CR_RIE |
UART010_CR_RTIE);
writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
port->membase + UART010_CR);
return 0;
}
@ -385,11 +367,12 @@ static void pl010_shutdown(struct uart_port *port)
/*
* disable all interrupts, disable the port
*/
UART_PUT_CR(port, 0);
writel(0, port->membase + UART010_CR);
/* disable break condition and fifos */
UART_PUT_LCRH(port, UART_GET_LCRH(port) &
~(UART01x_LCRH_BRK | UART01x_LCRH_FEN));
writel(readb(port->membase + UART010_LCRH) &
~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
port->membase + UART010_LCRH);
}
static void
@ -466,25 +449,25 @@ pl010_set_termios(struct uart_port *port, struct termios *termios,
port->ignore_status_mask |= UART_DUMMY_RSR_RX;
/* first, disable everything */
old_cr = UART_GET_CR(port) & ~UART010_CR_MSIE;
old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
if (UART_ENABLE_MS(port, termios->c_cflag))
old_cr |= UART010_CR_MSIE;
UART_PUT_CR(port, 0);
writel(0, port->membase + UART010_CR);
/* Set baud rate */
quot -= 1;
UART_PUT_LCRM(port, ((quot & 0xf00) >> 8));
UART_PUT_LCRL(port, (quot & 0xff));
writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
writel(quot & 0xff, port->membase + UART010_LCRL);
/*
* ----------v----------v----------v----------v-----
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
* ----------^----------^----------^----------^-----
*/
UART_PUT_LCRH(port, lcr_h);
UART_PUT_CR(port, old_cr);
writel(lcr_h, port->membase + UART010_LCRH);
writel(old_cr, port->membase + UART010_CR);
spin_unlock_irqrestore(&port->lock, flags);
}
@ -593,9 +576,13 @@ static struct uart_amba_port amba_ports[UART_NR] = {
static void pl010_console_putchar(struct uart_port *port, int ch)
{
while (!UART_TX_READY(UART_GET_FR(port)))
unsigned int status;
do {
status = readb(port->membase + UART01x_FR);
barrier();
UART_PUT_CHAR(port, ch);
} while (!UART_TX_READY(status));
writel(ch, port->membase + UART01x_DR);
}
static void
@ -607,8 +594,8 @@ pl010_console_write(struct console *co, const char *s, unsigned int count)
/*
* First save the CR then disable the interrupts
*/
old_cr = UART_GET_CR(port);
UART_PUT_CR(port, UART01x_CR_UARTEN);
old_cr = readb(port->membase + UART010_CR);
writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
uart_console_write(port, s, count, pl010_console_putchar);
@ -617,18 +604,19 @@ pl010_console_write(struct console *co, const char *s, unsigned int count)
* and restore the TCR
*/
do {
status = UART_GET_FR(port);
status = readb(port->membase + UART01x_FR);
barrier();
} while (status & UART01x_FR_BUSY);
UART_PUT_CR(port, old_cr);
writel(old_cr, port->membase + UART010_CR);
}
static void __init
pl010_console_get_options(struct uart_port *port, int *baud,
int *parity, int *bits)
{
if (UART_GET_CR(port) & UART01x_CR_UARTEN) {
if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
unsigned int lcr_h, quot;
lcr_h = UART_GET_LCRH(port);
lcr_h = readb(port->membase + UART010_LCRH);
*parity = 'n';
if (lcr_h & UART01x_LCRH_PEN) {
@ -643,7 +631,7 @@ pl010_console_get_options(struct uart_port *port, int *baud,
else
*bits = 8;
quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8;
quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
*baud = port->uartclk / (16 * (quot + 1));
}
}

1
include/linux/serial_8250.h
View File

@ -37,6 +37,7 @@ enum {
PLAT8250_DEV_LEGACY = -1,
PLAT8250_DEV_PLATFORM,
PLAT8250_DEV_PLATFORM1,
PLAT8250_DEV_PLATFORM2,
PLAT8250_DEV_FOURPORT,
PLAT8250_DEV_ACCENT,
PLAT8250_DEV_BOCA,