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drm/i915/tgl: Add DPLL registers

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On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.

v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-21-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi 2019-07-11 10:31:14 -07:00
parent d757535e31
commit 36ca5335f2
2 changed files with 36 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -3119,8 +3119,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
if (INTEL_GEN(dev_priv) >= 12) {
hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
} else {
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
}
ret = true;
out:
@ -3154,10 +3159,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
POSTING_READ(ICL_DPLL_CFGCR1(id));
if (INTEL_GEN(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
cfgcr0_reg = ICL_DPLL_CFGCR0(id);
cfgcr1_reg = ICL_DPLL_CFGCR1(id);
}
I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,

17
drivers/gpu/drm/i915/i915_reg.h
View File

@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@ -9955,6 +9956,22 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
#define _TGL_DPLL0_CFGCR0 0x164284
#define _TGL_DPLL1_CFGCR0 0x16428C
/* TODO: add DPLL4 */
#define _TGL_TBTPLL_CFGCR0 0x16429C
#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
_TGL_DPLL1_CFGCR0, \
_TGL_TBTPLL_CFGCR0)
#define _TGL_DPLL0_CFGCR1 0x164288
#define _TGL_DPLL1_CFGCR1 0x164290
/* TODO: add DPLL4 */
#define _TGL_TBTPLL_CFGCR1 0x1642A0
#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */