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arm64: dts: renesas: r9a07g044: Add OPP table

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Add OPP table for RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-11-24 15:43:16 +00:00 committed by Geert Uytterhoeven
parent 7744b393c9
commit 36959e2108
1 changed files with 31 additions and 0 deletions
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31
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
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@ -42,6 +42,33 @@
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -63,6 +90,8 @@
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@ -71,6 +100,8 @@
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {