forked from Minki/linux
x86/MCE/AMD, EDAC/mce_amd: Remove struct smca_hwid.xec_bitmap
The Extended Error Code Bitmap (xec_bitmap) for a Scalable MCA bank type was intended to be used by the kernel to filter out invalid error codes on a system. However, this is unnecessary after a few product releases because the hardware will only report valid error codes. Thus, there's no need for it with future systems. Remove the xec_bitmap field and all references to it. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200720145353.43924-1-Yazen.Ghannam@amd.com
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@ -328,7 +328,6 @@ enum smca_bank_types {
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struct smca_hwid {
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unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
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u32 hwid_mcatype; /* (hwid,mcatype) tuple */
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u32 xec_bitmap; /* Bitmap of valid ExtErrorCodes; current max is 21. */
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u8 count; /* Number of instances. */
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};
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@ -132,49 +132,49 @@ static enum smca_bank_types smca_get_bank_type(unsigned int bank)
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}
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static struct smca_hwid smca_hwid_mcatypes[] = {
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/* { bank_type, hwid_mcatype, xec_bitmap } */
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/* { bank_type, hwid_mcatype } */
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/* Reserved type */
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{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
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{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
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/* ZN Core (HWID=0xB0) MCA types */
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{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF },
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{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10), 0xFFFFFF },
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{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
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{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
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{ SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF },
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{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
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{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
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{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
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{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
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{ SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
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/* HWID 0xB0 MCATYPE 0x4 is Reserved */
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{ SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0xFFF },
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{ SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F },
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{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
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{ SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
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{ SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
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{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
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/* Data Fabric MCA types */
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{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF },
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{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0x1F },
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{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2), 0x3FFF },
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{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
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{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
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{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
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/* Unified Memory Controller MCA type */
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{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0xFF },
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{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
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/* Parameter Block MCA type */
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{ SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 },
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{ SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
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/* Platform Security Processor MCA type */
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{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 },
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{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1), 0x3FFFF },
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{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
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{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
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/* System Management Unit MCA type */
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{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 },
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{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1), 0x7FF },
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{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
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{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
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/* Microprocessor 5 Unit MCA type */
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{ SMCA_MP5, HWID_MCATYPE(0x01, 0x2), 0x3FF },
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{ SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
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/* Northbridge IO Unit MCA type */
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{ SMCA_NBIO, HWID_MCATYPE(0x18, 0x0), 0x1F },
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{ SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
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/* PCI Express Unit MCA type */
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{ SMCA_PCIE, HWID_MCATYPE(0x46, 0x0), 0x1F },
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{ SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
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};
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struct smca_bank smca_banks[MAX_NR_BANKS];
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@ -990,10 +990,8 @@ static void decode_smca_error(struct mce *m)
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pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);
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/* Only print the decode of valid error codes */
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if (xec < smca_mce_descs[bank_type].num_descs &&
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(hwid->xec_bitmap & BIT_ULL(xec))) {
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if (xec < smca_mce_descs[bank_type].num_descs)
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pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);
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}
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if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
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decode_dram_ecc(cpu_to_node(m->extcpu), m);
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