forked from Minki/linux
mtd: nand: davinci: rely on generic DT parsing done in nand_scan_ident()
The core now takes care of parsing generic DT properties in nand_scan_ident() when nand_set_flash_node() has been called. Rely on this initialization instead of calling of_get_nand_xxx() manually. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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f05f6a10fb
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363b5db212
@ -34,7 +34,6 @@
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#include <linux/slab.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/of_mtd.h>
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#include <linux/platform_data/mtd-davinci.h>
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#include <linux/platform_data/mtd-davinci-aemif.h>
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@ -559,8 +558,6 @@ static struct davinci_nand_pdata
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"ti,davinci-mask-chipsel", &prop))
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pdata->mask_chipsel = prop;
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if (!of_property_read_string(pdev->dev.of_node,
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"nand-ecc-mode", &mode) ||
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!of_property_read_string(pdev->dev.of_node,
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"ti,davinci-ecc-mode", &mode)) {
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if (!strncmp("none", mode, 4))
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pdata->ecc_mode = NAND_ECC_NONE;
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@ -573,14 +570,11 @@ static struct davinci_nand_pdata
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"ti,davinci-ecc-bits", &prop))
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pdata->ecc_bits = prop;
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prop = of_get_nand_bus_width(pdev->dev.of_node);
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if (0 < prop || !of_property_read_u32(pdev->dev.of_node,
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"ti,davinci-nand-buswidth", &prop))
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if (prop == 16)
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pdata->options |= NAND_BUSWIDTH_16;
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if (!of_property_read_u32(pdev->dev.of_node,
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"ti,davinci-nand-buswidth", &prop) && prop == 16)
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pdata->options |= NAND_BUSWIDTH_16;
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if (of_property_read_bool(pdev->dev.of_node,
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"nand-on-flash-bbt") ||
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of_property_read_bool(pdev->dev.of_node,
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"ti,davinci-nand-use-bbt"))
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pdata->bbt_options = NAND_BBT_USE_FLASH;
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@ -610,7 +604,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
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void __iomem *base;
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int ret;
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uint32_t val;
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nand_ecc_modes_t ecc_mode;
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struct mtd_info *mtd;
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pdata = nand_davinci_get_pdata(pdev);
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@ -694,10 +687,41 @@ static int nand_davinci_probe(struct platform_device *pdev)
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info->chip.write_buf = nand_davinci_write_buf;
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/* Use board-specific ECC config */
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ecc_mode = pdata->ecc_mode;
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info->chip.ecc.mode = pdata->ecc_mode;
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ret = -EINVAL;
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switch (ecc_mode) {
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info->clk = devm_clk_get(&pdev->dev, "aemif");
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if (IS_ERR(info->clk)) {
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ret = PTR_ERR(info->clk);
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dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(info->clk);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
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ret);
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goto err_clk_enable;
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}
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spin_lock_irq(&davinci_nand_lock);
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/* put CSxNAND into NAND mode */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val |= BIT(info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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spin_unlock_irq(&davinci_nand_lock);
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/* Scan to find existence of the device(s) */
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ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
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goto err;
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}
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switch (info->chip.ecc.mode) {
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case NAND_ECC_NONE:
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case NAND_ECC_SOFT:
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pdata->ecc_bits = 0;
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@ -736,37 +760,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
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default:
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return -EINVAL;
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}
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info->chip.ecc.mode = ecc_mode;
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info->clk = devm_clk_get(&pdev->dev, "aemif");
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if (IS_ERR(info->clk)) {
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ret = PTR_ERR(info->clk);
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dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(info->clk);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
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ret);
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goto err_clk_enable;
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}
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spin_lock_irq(&davinci_nand_lock);
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/* put CSxNAND into NAND mode */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val |= BIT(info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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spin_unlock_irq(&davinci_nand_lock);
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/* Scan to find existence of the device(s) */
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ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
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goto err;
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}
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/* Update ECC layout if needed ... for 1-bit HW ECC, the default
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* is OK, but it allocates 6 bytes when only 3 are needed (for
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@ -820,7 +813,7 @@ err:
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err_clk_enable:
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spin_lock_irq(&davinci_nand_lock);
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if (ecc_mode == NAND_ECC_HW_SYNDROME)
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if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
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ecc4_busy = false;
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spin_unlock_irq(&davinci_nand_lock);
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return ret;
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