forked from Minki/linux
Merge branch 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6
* 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6: intel_idle: Voluntary leave_mm before entering deeper acpi_idle: add missing \n to printk intel_idle: add missing __percpu markup intel_idle: Change mode 755 => 644 cpuidle: Fix typos intel_idle: PCI quirk to prevent Lenovo Ideapad s10-3 boot hang
This commit is contained in:
commit
35ec42167b
@ -850,7 +850,7 @@ static int __init acpi_processor_init(void)
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printk(KERN_DEBUG "ACPI: %s registered with cpuidle\n",
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acpi_idle_driver.name);
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} else {
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printk(KERN_DEBUG "ACPI: acpi_idle yielding to %s",
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printk(KERN_DEBUG "ACPI: acpi_idle yielding to %s\n",
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cpuidle_get_driver()->name);
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}
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@ -80,7 +80,7 @@
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* Limiting Performance Impact
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* ---------------------------
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* C states, especially those with large exit latencies, can have a real
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* noticable impact on workloads, which is not acceptable for most sysadmins,
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* noticeable impact on workloads, which is not acceptable for most sysadmins,
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* and in addition, less performance has a power price of its own.
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*
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* As a general rule of thumb, menu assumes that the following heuristic
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20
drivers/idle/intel_idle.c
Executable file → Normal file
20
drivers/idle/intel_idle.c
Executable file → Normal file
@ -83,7 +83,7 @@ static unsigned int mwait_substates;
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/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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static unsigned int lapic_timer_reliable_states;
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static struct cpuidle_device *intel_idle_cpuidle_devices;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
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static struct cpuidle_state *cpuidle_state_table;
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@ -108,7 +108,7 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "NHM-C3",
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.desc = "MWAIT 0x10",
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.driver_data = (void *) 0x10,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.power_usage = 500,
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.target_residency = 80,
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@ -117,7 +117,7 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "NHM-C6",
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.desc = "MWAIT 0x20",
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.driver_data = (void *) 0x20,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.power_usage = 350,
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.target_residency = 800,
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@ -149,7 +149,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "ATM-C4",
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.desc = "MWAIT 0x30",
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.driver_data = (void *) 0x30,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 100,
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.power_usage = 250,
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.target_residency = 400,
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@ -159,7 +159,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "ATM-C6",
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.desc = "MWAIT 0x40",
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.driver_data = (void *) 0x40,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.power_usage = 150,
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.target_residency = 800,
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@ -185,6 +185,16 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
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local_irq_disable();
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/*
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* If the state flag indicates that the TLB will be flushed or if this
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* is the deepest c-state supported, do a voluntary leave mm to avoid
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* costly and mostly unnecessary wakeups for flushing the user TLB's
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* associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED ||
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(&dev->states[dev->state_count - 1] == state))
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leave_mm(cpu);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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@ -162,6 +162,26 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_d
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
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/*
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* Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
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* for some HT machines to use C4 w/o hanging.
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*/
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static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
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{
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u32 pmbase;
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u16 pm1a;
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pci_read_config_dword(dev, 0x40, &pmbase);
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pmbase = pmbase & 0xff80;
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pm1a = inw(pmbase);
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if (pm1a & 0x10) {
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dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
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outw(0x10, pmbase);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
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/*
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* Chipsets where PCI->PCI transfers vanish or hang
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*/
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@ -53,6 +53,7 @@ struct cpuidle_state {
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#define CPUIDLE_FLAG_BALANCED (0x40) /* medium latency, moderate savings */
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#define CPUIDLE_FLAG_DEEP (0x80) /* high latency, large savings */
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#define CPUIDLE_FLAG_IGNORE (0x100) /* ignore during this idle period */
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#define CPUIDLE_FLAG_TLB_FLUSHED (0x200) /* tlb will be flushed */
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#define CPUIDLE_DRIVER_FLAGS_MASK (0xFFFF0000)
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