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[media] e4000: fix PLL calc bug on 32-bit arch

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Fix long-lasting bug that causes tuning failure of some frequencies
on 32-bit arch.
Special thanks goes to Damien CABROL who finally find root of the bug.
Also big thanks to Jacek Konieczny for donating "non-working" device.

[crope@iki.fi: fix trivial merge conflict]
[m.chehab@samsung.com: add missing header file]
Reported-by: Jacek Konieczny <jajcus@jajcus.net>
Reported-by: Torsten Seyffarth <t.seyffarth@gmx.de>
Reported-by: Jan Taegert <jantaegert@gmx.net>
Reported-by: Damien CABROL <cabrol.damien@free.fr>
Tested-by: Damien CABROL <cabrol.damien@free.fr>
Tested-by: Jan Taegert <jantaegert@gmx.net>
Signed-off-by: Antti Palosaari <crope@iki.fi>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Antti Palosaari 2013-09-02 13:06:13 -03:00 committed by Mauro Carvalho Chehab
parent 1558ec837f
commit 35c00c98a2
1 changed files with 2 additions and 1 deletions
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3
drivers/media/tuners/e4000.c
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@ -19,6 +19,7 @@
*/
#include "e4000_priv.h"
#include <linux/math64.h>
/* write multiple registers */
static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
@ -233,7 +234,7 @@ static int e4000_set_params(struct dvb_frontend *fe)
* or more.
*/
f_vco = c->frequency * e4000_pll_lut[i].mul;
sigma_delta = 0x10000UL * (f_vco % priv->cfg->clock) / priv->cfg->clock;
sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock);
buf[0] = f_vco / priv->cfg->clock;
buf[1] = (sigma_delta >> 0) & 0xff;
buf[2] = (sigma_delta >> 8) & 0xff;