forked from Minki/linux
sh: Tidy up dependencies for SH-2 build.
SH-2 can presently get in to some pretty bogus states, so we tidy up the dependencies a bit and get it all building again. This gets us a bit closer to a functional allyesconfig and allmodconfig, though there are still a few things to fix up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
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54039591ce
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357d59469c
@ -55,8 +55,21 @@ config GENERIC_TIME
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config GENERIC_CLOCKEVENTS
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def_bool n
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config SYS_SUPPORTS_PM
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bool
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config SYS_SUPPORTS_APM_EMULATION
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bool
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select SYS_SUPPORTS_PM
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config SYS_SUPPORTS_SMP
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bool
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config SYS_SUPPORTS_NUMA
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bool
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config SYS_SUPPORTS_PCI
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bool
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config ARCH_MAY_HAVE_PC_FDC
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bool
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@ -102,7 +115,7 @@ endchoice
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config SH_FPU
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bool "FPU support"
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depends on !CPU_SH3
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depends on CPU_SH4
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default y
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help
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Selecting this option will enable support for SH processors that
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@ -236,6 +249,7 @@ config SH_7751_SOLUTION_ENGINE
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config SH_7780_SOLUTION_ENGINE
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bool "SolutionEngine7780"
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select SOLUTION_ENGINE
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select SYS_SUPPORTS_PCI
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depends on CPU_SUBTYPE_SH7780
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help
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Select 7780 SolutionEngine if configuring for a Renesas SH7780
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@ -275,20 +289,16 @@ config SH_7751_SYSTEMH
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config SH_HP6XX
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bool "HP6XX"
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select SYS_SUPPORTS_APM_EMULATION
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select HD6446X_SERIES
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depends on CPU_SUBTYPE_SH7709
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help
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Select HP6XX if configuring for a HP jornada HP6xx.
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More information (hardware only) at
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<http://www.hp.com/jornada/>.
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config SH_SATURN
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bool "Saturn"
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depends on CPU_SUBTYPE_SH7604
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help
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Select Saturn if configuring for a SEGA Saturn.
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config SH_DREAMCAST
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bool "Dreamcast"
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select SYS_SUPPORTS_PCI
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depends on CPU_SUBTYPE_SH7091
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help
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Select Dreamcast if configuring for a SEGA Dreamcast.
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@ -307,6 +317,7 @@ config SH_MPC1211
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config SH_SH03
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bool "Interface CTP/PCI-SH03"
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depends on CPU_SUBTYPE_SH7751 && BROKEN
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select SYS_SUPPORTS_PCI
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help
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CTP/PCI-SH03 is a CPU module computer that is produced
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by Interface Corporation.
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@ -315,6 +326,7 @@ config SH_SH03
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config SH_SECUREEDGE5410
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bool "SecureEdge5410"
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depends on CPU_SUBTYPE_SH7751R
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select SYS_SUPPORTS_PCI
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help
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Select SecureEdge5410 if configuring for a SnapGear SH board.
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This includes both the OEM SecureEdge products as well as the
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@ -337,6 +349,7 @@ config SH_7710VOIPGW
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config SH_RTS7751R2D
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bool "RTS7751R2D"
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depends on CPU_SUBTYPE_SH7751R
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select SYS_SUPPORTS_PCI
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help
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Select RTS7751R2D if configuring for a Renesas Technology
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Sales SH-Graphics board.
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@ -344,6 +357,7 @@ config SH_RTS7751R2D
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config SH_HIGHLANDER
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bool "Highlander"
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depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
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select SYS_SUPPORTS_PCI
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config SH_EDOSK7705
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bool "EDOSK7705"
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@ -359,12 +373,14 @@ config SH_SH4202_MICRODEV
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config SH_LANDISK
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bool "LANDISK"
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depends on CPU_SUBTYPE_SH7751R
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select SYS_SUPPORTS_PCI
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help
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I-O DATA DEVICE, INC. "LANDISK Series" support.
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config SH_TITAN
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bool "TITAN"
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depends on CPU_SUBTYPE_SH7751R
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select SYS_SUPPORTS_PCI
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help
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Select Titan if you are configuring for a Nimble Microsystems
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NetEngine NP51R.
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@ -378,6 +394,7 @@ config SH_SHMIN
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config SH_LBOX_RE2
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bool "L-BOX RE2"
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depends on CPU_SUBTYPE_SH7751R
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select SYS_SUPPORTS_PCI
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help
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Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
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@ -481,8 +498,10 @@ config SH_PCLK_FREQ
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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default 0
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depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206
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default 6 if CPU_SUBTYPE_SH7206
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default 5 if CPU_SUBTYPE_SH7619
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default 0
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help
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MD2 - MD0 pin setting.
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@ -554,6 +573,7 @@ config CRASH_DUMP
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config SMP
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bool "Symmetric multi-processing support"
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depends on SYS_SUPPORTS_SMP
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---help---
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, like most personal computers, say N. If
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@ -617,6 +637,7 @@ config BOOT_LINK_OFFSET
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config UBC_WAKEUP
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bool "Wakeup UBC on startup"
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depends on CPU_SH4
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help
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Selecting this option will wakeup the User Break Controller (UBC) on
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startup. Although the UBC is left in an awake state when the processor
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@ -645,8 +666,8 @@ menu "Bus options"
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# we're not using PCMCIA, so we make it dependent on
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# PCMCIA outright. -- PFM.
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config ISA
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bool
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default y if PCMCIA
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def_bool y
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depends on PCMCIA && HD6446X_SERIES
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help
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Find out whether you have ISA slots on your motherboard. ISA is the
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name of a bus system, i.e. the way the CPU talks to the other stuff
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@ -701,7 +722,7 @@ source "fs/Kconfig.binfmt"
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endmenu
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menu "Power management options (EXPERIMENTAL)"
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depends on EXPERIMENTAL
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depends on EXPERIMENTAL && SYS_SUPPORTS_PM
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source kernel/power/Kconfig
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@ -86,6 +86,7 @@ config SH_KGDB
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bool "Include KGDB kernel debugger"
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select FRAME_POINTER
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select DEBUG_INFO
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depends on CPU_SH3 || CPU_SH4
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help
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Include in-kernel hooks for kgdb, the Linux kernel source level
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debugger. See <http://kgdb.sourceforge.net/> for more information.
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@ -13,10 +13,8 @@ config VOYAGERGX
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are additional GPIO bits that can be used to interface to
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external as well.
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# A board must have defined HD6446X_SERIES in order to see these
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config HD6446X_SERIES
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bool "HD6446x support"
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default n
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bool
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choice
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prompt "HD6446x options"
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@ -25,7 +23,6 @@ choice
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config HD64461
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bool "Hitachi HD64461 companion chip support"
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depends on CPU_SUBTYPE_SH7709
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---help---
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The Hitachi HD64461 provides an interface for
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the SH7709 CPU, supporting a LCD controller,
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@ -40,7 +37,6 @@ config HD64461
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config HD64465
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bool "Hitachi HD64465 companion chip support"
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depends on CPU_SUBTYPE_SH7750
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---help---
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The Hitachi HD64465 provides an interface for
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the SH7750 CPU, supporting a LCD controller,
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@ -1,5 +1,6 @@
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config PCI
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bool "PCI support"
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depends on SYS_SUPPORTS_PCI
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help
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Find out whether you have a PCI motherboard. PCI is the name of a
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bus system, i.e. the way the CPU talks to the other stuff inside
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@ -21,8 +21,7 @@
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#include <asm/cacheflush.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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extern void detect_cpu_and_cache_system(void);
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#include <asm/ubc.h>
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/*
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* Generic wrapper for command line arguments to disable on-chip
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@ -152,15 +151,6 @@ static void __init cache_init(void)
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flags |= CCR_CACHE_CB;
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#endif
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#ifdef CONFIG_SH_OCRAM
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/* Turn on OCRAM -- halve the OC */
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flags |= CCR_CACHE_ORA;
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current_cpu_data.dcache.sets >>= 1;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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#endif
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ctrl_outl(flags, CCR);
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back_to_P1();
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}
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@ -269,7 +259,6 @@ asmlinkage void __init sh_cpu_init(void)
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}
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#endif
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#ifdef CONFIG_UBC_WAKEUP
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/*
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* Some brain-damaged loaders decided it would be a good idea to put
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* the UBC to sleep. This causes some issues when it comes to things
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@ -277,7 +266,5 @@ asmlinkage void __init sh_cpu_init(void)
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* we wake it up and hope that all is well.
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*/
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ubc_wakeup();
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#endif
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speculative_execution_init();
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}
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@ -9,9 +9,8 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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ctrl_outl(pc, UBC_BARA);
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#ifdef CONFIG_MMU
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/* We don't have any ASID settings for the SH-2! */
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if (current_cpu_data.type != CPU_SH7604)
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ctrl_outb(asid, UBC_BASRA);
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ctrl_outb(asid, UBC_BASRA);
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#endif
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ctrl_outl(0, UBC_BAMRA);
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@ -48,6 +48,7 @@ choice
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config CPU_SUBTYPE_SH7619
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bool "Support SH7619 processor"
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select CPU_SH2
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select CPU_HAS_IPR_IRQ
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# SH-2A Processor Support
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@ -208,6 +209,7 @@ config CPU_SUBTYPE_SH7722
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select CPU_SHX2
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select CPU_HAS_IPR_IRQ
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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endchoice
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@ -292,7 +294,7 @@ config VSYSCALL
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config NUMA
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bool "Non Uniform Memory Access (NUMA) Support"
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depends on MMU && SPARSEMEM && EXPERIMENTAL
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depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
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default n
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help
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Some SH systems have many various memories scattered around
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@ -308,6 +310,7 @@ config NODES_SHIFT
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config ARCH_FLATMEM_ENABLE
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def_bool y
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depends on !NUMA
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config ARCH_SPARSEMEM_ENABLE
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def_bool y
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@ -419,15 +422,4 @@ config SH_WRITETHROUGH
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If unsure, say N.
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config SH_OCRAM
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bool "Operand Cache RAM (OCRAM) support"
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help
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Selecting this option will automatically tear down the number of
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sets in the dcache by half, which in turn exposes a memory range.
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The addresses for the OC RAM base will vary according to the
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processor version. Consult vendor documentation for specifics.
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If unsure, say N.
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endmenu
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@ -300,6 +300,7 @@ int remove_memory(u64 start, u64 size)
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}
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EXPORT_SYMBOL_GPL(remove_memory);
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#ifdef CONFIG_NUMA
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int memory_add_physaddr_to_nid(u64 addr)
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{
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/* Node 0 for now.. */
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@ -307,3 +308,4 @@ int memory_add_physaddr_to_nid(u64 addr)
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}
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EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
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#endif
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#endif
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#define __ASM_SH_CACHE_H
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#ifdef __KERNEL__
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#include <linux/init.h>
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#include <asm/cpu/cache.h>
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#define SH_CACHE_VALID 1
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@ -48,6 +49,9 @@ struct cache_info {
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unsigned long flags;
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};
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int __init detect_cpu_and_cache_system(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_CACHE_H */
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#define HD64461_NIRR 0x15000
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#define HD64461_NIMR 0x15002
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#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
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#define HD64461_IRQBASE 64
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#define HD64461_IRQ_NUM 16
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#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
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regs->sr &= ~SR_FD;
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}
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#ifdef CONFIG_CPU_SH4
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extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
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#else
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#define save_fpu(tsk) do { } while (0)
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#endif
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#define unlazy_fpu(tsk, regs) do { \
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if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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/*
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* Jump to P2 area.
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#define BRCR_UBDE (1 << 0)
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#ifndef __ASSEMBLY__
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/* arch/sh/kernel/ubc.S */
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extern void ubc_wakeup(void);
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/* arch/sh/kernel/cpu/ubc.S */
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extern void ubc_sleep(void);
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#ifdef CONFIG_UBC_WAKEUP
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extern void ubc_wakeup(void);
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#else
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#define ubc_wakeup() do { } while (0)
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#endif
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#endif
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#endif /* __KERNEL__ */
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Block a user