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i2c: davinci: Optimize clock generation on Keystone SoC

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According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
additive part of frequency divisors (referred as "d" in the code and datasheet)
always equals to 6, independent of module clock prescaler.

                         module clock frequency
master clock frequency = ----------------------
                         (ICCL + 6) + (ICCH + 6)

It was not the case with original Davinci IP. Introduce new compatible property
"ti,keystone-i2c", which triggers special handling in the driver.

Without this change Keystone-based systems (having 204.8MHz input clock) choose
prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz
instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz.
This gives ~11% transfer rate increase.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com>
Tested-by: Lukasz Gemborowski <lukasz.gemborowski@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Alexander Sverdlin
2015-09-14 11:03:50 +02:00
committed by Wolfram Sang
parent 064181b00e
commit 35780e860f
2 changed files with 11 additions and 3 deletions
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6
Documentation/devicetree/bindings/i2c/i2c-davinci.txt
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@@ -1,10 +1,10 @@
* Texas Instruments Davinci I2C
* Texas Instruments Davinci/Keystone I2C
This file provides information, what the device node for the
davinci i2c interface contain.
davinci/keystone i2c interface contains.
Required properties:
- compatible: "ti,davinci-i2c";
- compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
- reg : Offset and length of the register set for the device
Recommended properties :