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mmc: sunxi: add support for A100 mmc controller

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This patch adds support for A100 MMC controller, which use word address
for internal dma.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20201211011934.6171-10-andre.przywara@arm.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Yangtao Li 2020-12-11 01:19:22 +00:00 committed by Ulf Hansson
parent b79ee3852c
commit 3536b82e58
1 changed files with 25 additions and 3 deletions
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28
drivers/mmc/host/sunxi-mmc.c
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@ -245,6 +245,7 @@ struct sunxi_idma_des {
struct sunxi_mmc_cfg { struct sunxi_mmc_cfg {
u32 idma_des_size_bits; u32 idma_des_size_bits;
u32 idma_des_shift;
const struct sunxi_mmc_clk_delay *clk_delays; const struct sunxi_mmc_clk_delay *clk_delays;
/* does the IP block support autocalibration? */ /* does the IP block support autocalibration? */
@ -344,7 +345,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
/* Enable CEATA support */ /* Enable CEATA support */
mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
/* Set DMA descriptor list base address */ /* Set DMA descriptor list base address */
mmc_writel(host, REG_DLBA, host->sg_dma); mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
rval = mmc_readl(host, REG_GCTRL); rval = mmc_readl(host, REG_GCTRL);
rval |= SDXC_INTERRUPT_ENABLE_BIT; rval |= SDXC_INTERRUPT_ENABLE_BIT;
@ -374,8 +375,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
next_desc += sizeof(struct sunxi_idma_des); next_desc += sizeof(struct sunxi_idma_des);
pdes[i].buf_addr_ptr1 = pdes[i].buf_addr_ptr1 =
cpu_to_le32(sg_dma_address(&data->sg[i])); cpu_to_le32(sg_dma_address(&data->sg[i]) >>
pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); host->cfg->idma_des_shift);
pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
host->cfg->idma_des_shift);
} }
pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
@ -1179,6 +1182,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.needs_new_timings = true, .needs_new_timings = true,
}; };
static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
.idma_des_size_bits = 16,
.idma_des_shift = 2,
.clk_delays = NULL,
.can_calibrate = true,
.mask_data0 = true,
.needs_new_timings = true,
};
static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
.idma_des_size_bits = 13,
.idma_des_shift = 2,
.clk_delays = NULL,
.can_calibrate = true,
.needs_new_timings = true,
};
static const struct of_device_id sunxi_mmc_of_match[] = { static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
@ -1187,6 +1207,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
{ /* sentinel */ } { /* sentinel */ }
}; };
MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);