forked from Minki/linux
ARM: S3C64XX: Move headers into machine include directory
Move the register and GPIO definition files from plat-s3c64xx into the machine include direcotry as they are unlikely to be reused outside mach-s3c64xx. This move includes removing the empty <mach/regs-clock.h> and replacing it with the <plat/regs-clock.h> implementation. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
parent
2f6c2ac1d9
commit
3501c9ae9f
@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,4 +1,4 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
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/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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@ -1,16 +1,156 @@
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/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
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/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - clock register compatibility with s3c24xx
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* S3C64XX clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <plat/regs-clock.h>
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#ifndef __PLAT_REGS_CLOCK_H
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#define __PLAT_REGS_CLOCK_H __FILE__
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#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
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#define S3C_APLL_LOCK S3C_CLKREG(0x00)
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#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
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#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
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#define S3C_APLL_CON S3C_CLKREG(0x0C)
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#define S3C_MPLL_CON S3C_CLKREG(0x10)
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#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
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#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
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#define S3C_CLK_SRC S3C_CLKREG(0x1C)
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#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
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#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
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#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
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#define S3C_CLK_OUT S3C_CLKREG(0x2C)
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#define S3C_HCLK_GATE S3C_CLKREG(0x30)
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#define S3C_PCLK_GATE S3C_CLKREG(0x34)
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#define S3C_SCLK_GATE S3C_CLKREG(0x38)
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#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
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/* CLKDIV0 */
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#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
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#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
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#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
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#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
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#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
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#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
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#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
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#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
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#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
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#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
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#define S3C6400_CLKDIV0_ARM_SHIFT (0)
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/* HCLK GATE Registers */
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#define S3C_CLKCON_HCLK_3DSE (1<<31)
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#define S3C_CLKCON_HCLK_UHOST (1<<29)
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#define S3C_CLKCON_HCLK_SECUR (1<<28)
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#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
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#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
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#define S3C_CLKCON_HCLK_IROM (1<<25)
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#define S3C_CLKCON_HCLK_DDR1 (1<<24)
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#define S3C_CLKCON_HCLK_DDR0 (1<<23)
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#define S3C_CLKCON_HCLK_MEM1 (1<<22)
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#define S3C_CLKCON_HCLK_MEM0 (1<<21)
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#define S3C_CLKCON_HCLK_USB (1<<20)
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#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
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#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
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#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
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#define S3C_CLKCON_HCLK_MDP (1<<16)
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#define S3C_CLKCON_HCLK_DHOST (1<<15)
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#define S3C_CLKCON_HCLK_IHOST (1<<14)
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#define S3C_CLKCON_HCLK_DMA1 (1<<13)
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#define S3C_CLKCON_HCLK_DMA0 (1<<12)
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#define S3C_CLKCON_HCLK_JPEG (1<<11)
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#define S3C_CLKCON_HCLK_CAMIF (1<<10)
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#define S3C_CLKCON_HCLK_SCALER (1<<9)
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#define S3C_CLKCON_HCLK_2D (1<<8)
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#define S3C_CLKCON_HCLK_TV (1<<7)
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#define S3C_CLKCON_HCLK_POST0 (1<<5)
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#define S3C_CLKCON_HCLK_ROT (1<<4)
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#define S3C_CLKCON_HCLK_LCD (1<<3)
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#define S3C_CLKCON_HCLK_TZIC (1<<2)
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#define S3C_CLKCON_HCLK_INTC (1<<1)
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#define S3C_CLKCON_HCLK_MFC (1<<0)
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/* PCLK GATE Registers */
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#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
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#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
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#define S3C_CLKCON_PCLK_SKEY (1<<24)
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#define S3C_CLKCON_PCLK_CHIPID (1<<23)
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#define S3C_CLKCON_PCLK_SPI1 (1<<22)
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#define S3C_CLKCON_PCLK_SPI0 (1<<21)
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#define S3C_CLKCON_PCLK_HSIRX (1<<20)
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#define S3C_CLKCON_PCLK_HSITX (1<<19)
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#define S3C_CLKCON_PCLK_GPIO (1<<18)
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#define S3C_CLKCON_PCLK_IIC (1<<17)
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#define S3C_CLKCON_PCLK_IIS1 (1<<16)
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#define S3C_CLKCON_PCLK_IIS0 (1<<15)
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#define S3C_CLKCON_PCLK_AC97 (1<<14)
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#define S3C_CLKCON_PCLK_TZPC (1<<13)
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#define S3C_CLKCON_PCLK_TSADC (1<<12)
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#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
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#define S3C_CLKCON_PCLK_IRDA (1<<10)
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#define S3C_CLKCON_PCLK_PCM1 (1<<9)
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#define S3C_CLKCON_PCLK_PCM0 (1<<8)
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#define S3C_CLKCON_PCLK_PWM (1<<7)
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#define S3C_CLKCON_PCLK_RTC (1<<6)
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#define S3C_CLKCON_PCLK_WDT (1<<5)
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#define S3C_CLKCON_PCLK_UART3 (1<<4)
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#define S3C_CLKCON_PCLK_UART2 (1<<3)
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#define S3C_CLKCON_PCLK_UART1 (1<<2)
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#define S3C_CLKCON_PCLK_UART0 (1<<1)
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#define S3C_CLKCON_PCLK_MFC (1<<0)
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/* SCLK GATE Registers */
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#define S3C_CLKCON_SCLK_UHOST (1<<30)
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#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
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#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
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#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
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#define S3C_CLKCON_SCLK_MMC2 (1<<26)
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#define S3C_CLKCON_SCLK_MMC1 (1<<25)
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#define S3C_CLKCON_SCLK_MMC0 (1<<24)
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#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
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#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
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#define S3C_CLKCON_SCLK_SPI1 (1<<21)
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#define S3C_CLKCON_SCLK_SPI0 (1<<20)
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#define S3C_CLKCON_SCLK_DAC27 (1<<19)
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#define S3C_CLKCON_SCLK_TV27 (1<<18)
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#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
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#define S3C_CLKCON_SCLK_SCALER (1<<16)
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#define S3C_CLKCON_SCLK_LCD27 (1<<15)
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#define S3C_CLKCON_SCLK_LCD (1<<14)
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#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
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#define S3C6410_CLKCON_FIMC (1<<13)
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#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
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#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
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#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
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#define S3C_CLKCON_SCLK_POST0 (1<<10)
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#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
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#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
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#define S3C_CLKCON_SCLK_SECUR (1<<7)
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#define S3C_CLKCON_SCLK_IRDA (1<<6)
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#define S3C_CLKCON_SCLK_UART (1<<5)
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#define S3C_CLKCON_SCLK_ONENAND (1<<4)
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#define S3C_CLKCON_SCLK_MFC (1<<3)
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#define S3C_CLKCON_SCLK_CAM (1<<2)
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#define S3C_CLKCON_SCLK_JPEG (1<<1)
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/* CLKSRC */
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#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
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#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
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#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
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#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
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#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
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#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
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#define S3C6400_CLKSRC_MFC (1 << 4)
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#endif /* _PLAT_REGS_CLOCK_H */
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@ -49,8 +49,8 @@
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <plat/regs-gpio.h>
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#include <plat/regs-modem.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-modem.h>
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/* DM9000 */
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#define ANW6410_PA_DM9000 (0x18000000)
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#include <asm/mach-types.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-modem.h>
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#include <plat/regs-gpio.h>
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#include <plat/regs-sys.h>
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#include <plat/regs-srom.h>
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#include <mach/regs-modem.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-sys.h>
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#include <mach/regs-srom.h>
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#include <plat/iic.h>
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#include <plat/fb.h>
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#include <plat/gpio-cfg.h>
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@ -30,7 +30,7 @@
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#include <plat/cpu-freq.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-clock.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/cpu-freq.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-clock.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/regs-sys.h>
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#include <plat/regs-clock.h>
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#include <mach/regs-sys.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/audio.h>
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#include <plat/gpio-bank-c.h>
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#include <plat/gpio-bank-d.h>
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#include <plat/gpio-bank-e.h>
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#include <plat/gpio-bank-h.h>
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#include <plat/gpio-cfg.h>
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#include <mach/gpio-bank-c.h>
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#include <mach/gpio-bank-d.h>
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#include <mach/gpio-bank-e.h>
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#include <mach/gpio-bank-h.h>
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static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
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{
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switch (pdev->id) {
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#include <mach/dma.h>
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#include <mach/map.h>
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#include <mach/gpio.h>
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#include <mach/gpio-bank-c.h>
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#include <plat/spi-clocks.h>
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#include <plat/s3c64xx-spi.h>
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#include <plat/gpio-bank-c.h>
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#include <plat/gpio-cfg.h>
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#include <plat/irqs.h>
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@ -28,7 +28,7 @@
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#include <mach/irqs.h>
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#include <plat/dma-plat.h>
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#include <plat/regs-sys.h>
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#include <mach/regs-sys.h>
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#include <asm/hardware/pl080.h>
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@ -22,7 +22,7 @@
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#include <plat/regs-gpio.h>
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#include <mach/regs-gpio.h>
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||||
|
||||
/* GPIO bank summary:
|
||||
*
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
{
|
||||
|
||||
@ -1,156 +0,0 @@
|
||||
/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX clock register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_REGS_CLOCK_H
|
||||
#define __PLAT_REGS_CLOCK_H __FILE__
|
||||
|
||||
#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
|
||||
|
||||
#define S3C_APLL_LOCK S3C_CLKREG(0x00)
|
||||
#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
|
||||
#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
|
||||
#define S3C_APLL_CON S3C_CLKREG(0x0C)
|
||||
#define S3C_MPLL_CON S3C_CLKREG(0x10)
|
||||
#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
|
||||
#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
|
||||
#define S3C_CLK_SRC S3C_CLKREG(0x1C)
|
||||
#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
|
||||
#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
|
||||
#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
|
||||
#define S3C_CLK_OUT S3C_CLKREG(0x2C)
|
||||
#define S3C_HCLK_GATE S3C_CLKREG(0x30)
|
||||
#define S3C_PCLK_GATE S3C_CLKREG(0x34)
|
||||
#define S3C_SCLK_GATE S3C_CLKREG(0x38)
|
||||
#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
|
||||
|
||||
/* CLKDIV0 */
|
||||
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
|
||||
#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
|
||||
#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
|
||||
#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
|
||||
#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
|
||||
#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
|
||||
#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
|
||||
#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
|
||||
|
||||
#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
|
||||
#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
|
||||
#define S3C6400_CLKDIV0_ARM_SHIFT (0)
|
||||
|
||||
/* HCLK GATE Registers */
|
||||
#define S3C_CLKCON_HCLK_3DSE (1<<31)
|
||||
#define S3C_CLKCON_HCLK_UHOST (1<<29)
|
||||
#define S3C_CLKCON_HCLK_SECUR (1<<28)
|
||||
#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
|
||||
#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
|
||||
#define S3C_CLKCON_HCLK_IROM (1<<25)
|
||||
#define S3C_CLKCON_HCLK_DDR1 (1<<24)
|
||||
#define S3C_CLKCON_HCLK_DDR0 (1<<23)
|
||||
#define S3C_CLKCON_HCLK_MEM1 (1<<22)
|
||||
#define S3C_CLKCON_HCLK_MEM0 (1<<21)
|
||||
#define S3C_CLKCON_HCLK_USB (1<<20)
|
||||
#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
|
||||
#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
|
||||
#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
|
||||
#define S3C_CLKCON_HCLK_MDP (1<<16)
|
||||
#define S3C_CLKCON_HCLK_DHOST (1<<15)
|
||||
#define S3C_CLKCON_HCLK_IHOST (1<<14)
|
||||
#define S3C_CLKCON_HCLK_DMA1 (1<<13)
|
||||
#define S3C_CLKCON_HCLK_DMA0 (1<<12)
|
||||
#define S3C_CLKCON_HCLK_JPEG (1<<11)
|
||||
#define S3C_CLKCON_HCLK_CAMIF (1<<10)
|
||||
#define S3C_CLKCON_HCLK_SCALER (1<<9)
|
||||
#define S3C_CLKCON_HCLK_2D (1<<8)
|
||||
#define S3C_CLKCON_HCLK_TV (1<<7)
|
||||
#define S3C_CLKCON_HCLK_POST0 (1<<5)
|
||||
#define S3C_CLKCON_HCLK_ROT (1<<4)
|
||||
#define S3C_CLKCON_HCLK_LCD (1<<3)
|
||||
#define S3C_CLKCON_HCLK_TZIC (1<<2)
|
||||
#define S3C_CLKCON_HCLK_INTC (1<<1)
|
||||
#define S3C_CLKCON_HCLK_MFC (1<<0)
|
||||
|
||||
/* PCLK GATE Registers */
|
||||
#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
|
||||
#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
|
||||
#define S3C_CLKCON_PCLK_SKEY (1<<24)
|
||||
#define S3C_CLKCON_PCLK_CHIPID (1<<23)
|
||||
#define S3C_CLKCON_PCLK_SPI1 (1<<22)
|
||||
#define S3C_CLKCON_PCLK_SPI0 (1<<21)
|
||||
#define S3C_CLKCON_PCLK_HSIRX (1<<20)
|
||||
#define S3C_CLKCON_PCLK_HSITX (1<<19)
|
||||
#define S3C_CLKCON_PCLK_GPIO (1<<18)
|
||||
#define S3C_CLKCON_PCLK_IIC (1<<17)
|
||||
#define S3C_CLKCON_PCLK_IIS1 (1<<16)
|
||||
#define S3C_CLKCON_PCLK_IIS0 (1<<15)
|
||||
#define S3C_CLKCON_PCLK_AC97 (1<<14)
|
||||
#define S3C_CLKCON_PCLK_TZPC (1<<13)
|
||||
#define S3C_CLKCON_PCLK_TSADC (1<<12)
|
||||
#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
|
||||
#define S3C_CLKCON_PCLK_IRDA (1<<10)
|
||||
#define S3C_CLKCON_PCLK_PCM1 (1<<9)
|
||||
#define S3C_CLKCON_PCLK_PCM0 (1<<8)
|
||||
#define S3C_CLKCON_PCLK_PWM (1<<7)
|
||||
#define S3C_CLKCON_PCLK_RTC (1<<6)
|
||||
#define S3C_CLKCON_PCLK_WDT (1<<5)
|
||||
#define S3C_CLKCON_PCLK_UART3 (1<<4)
|
||||
#define S3C_CLKCON_PCLK_UART2 (1<<3)
|
||||
#define S3C_CLKCON_PCLK_UART1 (1<<2)
|
||||
#define S3C_CLKCON_PCLK_UART0 (1<<1)
|
||||
#define S3C_CLKCON_PCLK_MFC (1<<0)
|
||||
|
||||
/* SCLK GATE Registers */
|
||||
#define S3C_CLKCON_SCLK_UHOST (1<<30)
|
||||
#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
|
||||
#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
|
||||
#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
|
||||
#define S3C_CLKCON_SCLK_MMC2 (1<<26)
|
||||
#define S3C_CLKCON_SCLK_MMC1 (1<<25)
|
||||
#define S3C_CLKCON_SCLK_MMC0 (1<<24)
|
||||
#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
|
||||
#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
|
||||
#define S3C_CLKCON_SCLK_SPI1 (1<<21)
|
||||
#define S3C_CLKCON_SCLK_SPI0 (1<<20)
|
||||
#define S3C_CLKCON_SCLK_DAC27 (1<<19)
|
||||
#define S3C_CLKCON_SCLK_TV27 (1<<18)
|
||||
#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
|
||||
#define S3C_CLKCON_SCLK_SCALER (1<<16)
|
||||
#define S3C_CLKCON_SCLK_LCD27 (1<<15)
|
||||
#define S3C_CLKCON_SCLK_LCD (1<<14)
|
||||
#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
|
||||
#define S3C6410_CLKCON_FIMC (1<<13)
|
||||
#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
|
||||
#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
|
||||
#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
|
||||
#define S3C_CLKCON_SCLK_POST0 (1<<10)
|
||||
#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
|
||||
#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
|
||||
#define S3C_CLKCON_SCLK_SECUR (1<<7)
|
||||
#define S3C_CLKCON_SCLK_IRDA (1<<6)
|
||||
#define S3C_CLKCON_SCLK_UART (1<<5)
|
||||
#define S3C_CLKCON_SCLK_ONENAND (1<<4)
|
||||
#define S3C_CLKCON_SCLK_MFC (1<<3)
|
||||
#define S3C_CLKCON_SCLK_CAM (1<<2)
|
||||
#define S3C_CLKCON_SCLK_JPEG (1<<1)
|
||||
|
||||
/* CLKSRC */
|
||||
|
||||
#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
|
||||
#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
|
||||
#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
|
||||
#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
|
||||
#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
|
||||
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
|
||||
#define S3C6400_CLKSRC_MFC (1 << 4)
|
||||
|
||||
#endif /* _PLAT_REGS_CLOCK_H */
|
||||
@ -22,7 +22,7 @@
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#include <plat/regs-irqtype.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-timer.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
|
||||
@ -20,14 +20,14 @@
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/pm.h>
|
||||
#include <plat/regs-sys.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/regs-clock.h>
|
||||
#include <plat/regs-syscon-power.h>
|
||||
#include <plat/regs-gpio-memport.h>
|
||||
#include <mach/regs-sys.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-syscon-power.h>
|
||||
#include <mach/regs-gpio-memport.h>
|
||||
|
||||
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
|
||||
#include <plat/gpio-bank-n.h>
|
||||
#include <mach/gpio-bank-n.h>
|
||||
|
||||
void s3c_pm_debug_smdkled(u32 set, u32 clear)
|
||||
{
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
|
||||
#include <plat/regs-clock.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
@ -18,8 +18,8 @@
|
||||
struct platform_device; /* don't need the contents */
|
||||
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/gpio-bank-b.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/gpio-bank-b.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
|
||||
@ -18,8 +18,8 @@
|
||||
struct platform_device; /* don't need the contents */
|
||||
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/gpio-bank-b.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/gpio-bank-b.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* linux/0arch/arm/plat-s3c64xx/sleep.S
|
||||
/* linux/arch/arm/plat-s3c64xx/sleep.S
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
@ -19,8 +19,8 @@
|
||||
#undef S3C64XX_VA_GPIO
|
||||
#define S3C64XX_VA_GPIO (0x0)
|
||||
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/gpio-bank-n.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/gpio-bank-n.h>
|
||||
|
||||
#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user