forked from Minki/linux
dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
This patch adds the new binding documentation for system clock and functional clock on Mediatek MT8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-2-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chun-Jie Chen
Stephen Boyd
parent
6880fa6c56
commit
34d3ed3b9a
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek Functional Clock Controller for MT8195
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The clock architecture in Mediatek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices except apusys_pll provide clock gate control in different IP blocks.
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The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8195-scp_adsp
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- mediatek,mt8195-imp_iic_wrap_s
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- mediatek,mt8195-imp_iic_wrap_w
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- mediatek,mt8195-mfgcfg
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- mediatek,mt8195-vppsys0
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- mediatek,mt8195-wpesys
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- mediatek,mt8195-wpesys_vpp0
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- mediatek,mt8195-wpesys_vpp1
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- mediatek,mt8195-vppsys1
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- mediatek,mt8195-imgsys
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- mediatek,mt8195-imgsys1_dip_top
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- mediatek,mt8195-imgsys1_dip_nr
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- mediatek,mt8195-imgsys1_wpe
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- mediatek,mt8195-ipesys
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- mediatek,mt8195-camsys
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- mediatek,mt8195-camsys_rawa
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- mediatek,mt8195-camsys_yuva
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- mediatek,mt8195-camsys_rawb
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- mediatek,mt8195-camsys_yuvb
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- mediatek,mt8195-camsys_mraw
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- mediatek,mt8195-ccusys
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- mediatek,mt8195-vdecsys_soc
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- mediatek,mt8195-vdecsys
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- mediatek,mt8195-vdecsys_core1
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- mediatek,mt8195-vencsys
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- mediatek,mt8195-vencsys_core1
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- mediatek,mt8195-apusys_pll
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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scp_adsp: clock-controller@10720000 {
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compatible = "mediatek,mt8195-scp_adsp";
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reg = <0x10720000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_s: clock-controller@11d03000 {
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compatible = "mediatek,mt8195-imp_iic_wrap_s";
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reg = <0x11d03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_w: clock-controller@11e05000 {
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compatible = "mediatek,mt8195-imp_iic_wrap_w";
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reg = <0x11e05000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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mfgcfg: clock-controller@13fbf000 {
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compatible = "mediatek,mt8195-mfgcfg";
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reg = <0x13fbf000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vppsys0: clock-controller@14000000 {
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compatible = "mediatek,mt8195-vppsys0";
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reg = <0x14000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys: clock-controller@14e00000 {
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compatible = "mediatek,mt8195-wpesys";
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reg = <0x14e00000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys_vpp0: clock-controller@14e02000 {
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compatible = "mediatek,mt8195-wpesys_vpp0";
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reg = <0x14e02000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys_vpp1: clock-controller@14e03000 {
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compatible = "mediatek,mt8195-wpesys_vpp1";
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reg = <0x14e03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vppsys1: clock-controller@14f00000 {
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compatible = "mediatek,mt8195-vppsys1";
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reg = <0x14f00000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys: clock-controller@15000000 {
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compatible = "mediatek,mt8195-imgsys";
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reg = <0x15000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_dip_top: clock-controller@15110000 {
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compatible = "mediatek,mt8195-imgsys1_dip_top";
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reg = <0x15110000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_dip_nr: clock-controller@15130000 {
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compatible = "mediatek,mt8195-imgsys1_dip_nr";
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reg = <0x15130000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_wpe: clock-controller@15220000 {
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compatible = "mediatek,mt8195-imgsys1_wpe";
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reg = <0x15220000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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ipesys: clock-controller@15330000 {
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compatible = "mediatek,mt8195-ipesys";
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reg = <0x15330000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys: clock-controller@16000000 {
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compatible = "mediatek,mt8195-camsys";
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reg = <0x16000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawa: clock-controller@1604f000 {
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compatible = "mediatek,mt8195-camsys_rawa";
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reg = <0x1604f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_yuva: clock-controller@1606f000 {
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compatible = "mediatek,mt8195-camsys_yuva";
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reg = <0x1606f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawb: clock-controller@1608f000 {
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compatible = "mediatek,mt8195-camsys_rawb";
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reg = <0x1608f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_yuvb: clock-controller@160af000 {
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compatible = "mediatek,mt8195-camsys_yuvb";
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reg = <0x160af000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_mraw: clock-controller@16140000 {
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compatible = "mediatek,mt8195-camsys_mraw";
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reg = <0x16140000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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ccusys: clock-controller@17200000 {
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compatible = "mediatek,mt8195-ccusys";
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reg = <0x17200000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys_soc: clock-controller@1800f000 {
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compatible = "mediatek,mt8195-vdecsys_soc";
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reg = <0x1800f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys: clock-controller@1802f000 {
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compatible = "mediatek,mt8195-vdecsys";
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reg = <0x1802f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys_core1: clock-controller@1803f000 {
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compatible = "mediatek,mt8195-vdecsys_core1";
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reg = <0x1803f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vencsys: clock-controller@1a000000 {
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compatible = "mediatek,mt8195-vencsys";
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reg = <0x1a000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vencsys_core1: clock-controller@1b000000 {
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compatible = "mediatek,mt8195-vencsys_core1";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apusys_pll: clock-controller@190f3000 {
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compatible = "mediatek,mt8195-apusys_pll";
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reg = <0x190f3000 0x1000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,73 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek System Clock Controller for MT8195
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The clock architecture in Mediatek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys provides most of PLLs which generated from SoC 26m.
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The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8195-topckgen
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- mediatek,mt8195-infracfg_ao
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- mediatek,mt8195-apmixedsys
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- mediatek,mt8195-pericfg_ao
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8195-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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infracfg_ao: syscon@10001000 {
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compatible = "mediatek,mt8195-infracfg_ao", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8195-apmixedsys", "syscon";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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pericfg_ao: syscon@11003000 {
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compatible = "mediatek,mt8195-pericfg_ao", "syscon";
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reg = <0x11003000 0x1000>;
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#clock-cells = <1>;
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};
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