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MIPS: CI20: Add second percpu timer for SMP.

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1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2021-06-26 14:18:41 +08:00 committed by Thomas Bogendoerfer
parent 23c64447b3
commit 34c522a07c
1 changed files with 14 additions and 10 deletions
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24
arch/mips/boot/dts/ingenic/ci20.dts
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@ -118,6 +118,20 @@
assigned-clock-rates = <48000000>; assigned-clock-rates = <48000000>;
}; };
&tcu {
/*
* 750 kHz for the system timers and clocksource,
* use channel #0 and #1 for the per cpu system timers,
* and use channel #2 for the clocksource.
*
* 3000 kHz for the OST timer to provide a higher
* precision clocksource.
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
};
&mmc0 { &mmc0 {
status = "okay"; status = "okay";
@ -522,13 +536,3 @@
bias-disable; bias-disable;
}; };
}; };
&tcu {
/*
* 750 kHz for the system timer and clocksource,
* use channel #0 for the system timer, #1 for the clocksource.
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_OST>;
assigned-clock-rates = <750000>, <750000>, <3000000>;
};