forked from Minki/linux
CRIS: Additional mmu settings for ARTPEC-3
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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cd4f20110c
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@ -69,7 +69,13 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
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;;
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;; Note; 3 cycles is needed for a bank-select to take effect. Further;
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;; bank 1 is the instruction MMU, bank 2 is the data MMU.
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#ifndef CONFIG_ETRAX_VCS_SIM
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
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#elif !defined(CONFIG_ETRAX_VCS_SIM)
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move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
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@ -88,7 +94,39 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
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;; Enable certain page protections and setup linear mapping
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;; for f,e,c,b,4,0.
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#ifndef CONFIG_ETRAX_VCS_SIM
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;; ARTPEC-3:
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;; c,d used for linear kernel mapping, up to 512 MB
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;; e used for vmalloc
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;; f unused, but page mapped to get page faults
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;; ETRAX FS:
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;; c used for linear kernel mapping, up to 256 MB
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;; d used for vmalloc
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;; e,f used for memory-mapped NOR flash
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
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| REG_STATE(mmu, rw_mm_cfg, acc, on) \
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| REG_STATE(mmu, rw_mm_cfg, ex, on) \
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| REG_STATE(mmu, rw_mm_cfg, inv, on) \
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| REG_STATE(mmu, rw_mm_cfg, seg_f, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_e, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_d, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
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#elif !defined(CONFIG_ETRAX_VCS_SIM)
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move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
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| REG_STATE(mmu, rw_mm_cfg, acc, on) \
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| REG_STATE(mmu, rw_mm_cfg, ex, on) \
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