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drm/amdkfd: fix the wrong sdma instance query for renoir

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Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui
2020-08-11 13:54:56 +08:00
committed by Alex Deucher
parent 0a668aee0a
commit 34174b89bf
1 changed files with 22 additions and 9 deletions
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31
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
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@@ -195,19 +195,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
unsigned int engine_id, unsigned int engine_id,
unsigned int queue_id) unsigned int queue_id)
{ {
uint32_t sdma_engine_reg_base[2] = { uint32_t sdma_engine_reg_base = 0;
SOC15_REG_OFFSET(SDMA0, 0, uint32_t sdma_rlc_reg_offset;
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
SOC15_REG_OFFSET(SDMA1, 0, switch (engine_id) {
mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL default:
}; dev_warn(adev->dev,
uint32_t retval = sdma_engine_reg_base[engine_id] "Invalid sdma engine id (%d), using engine id 0\n",
engine_id);
fallthrough;
case 0:
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
case 1:
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
break;
}
sdma_rlc_reg_offset = sdma_engine_reg_base
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
queue_id, retval); queue_id, sdma_rlc_reg_offset);
return retval; return sdma_rlc_reg_offset;
} }
static inline struct v9_mqd *get_mqd(void *mqd) static inline struct v9_mqd *get_mqd(void *mqd)