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drm/radeon/cik: Add macrotile mode array query

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This is required to properly calculate the tiling parameters
in userspace.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2013-11-18 18:26:00 +09:00 committed by Alex Deucher
parent 1ddce27d8f
commit 32f79a8a82
5 changed files with 17 additions and 1 deletions
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3
drivers/gpu/drm/radeon/cik.c
View File

@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
gb_tile_moden = 0; gb_tile_moden = 0;
break; break;
} }
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
} }
} else if (num_pipe_configs == 4) { } else if (num_pipe_configs == 4) {
@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
gb_tile_moden = 0; gb_tile_moden = 0;
break; break;
} }
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
} }
} else if (num_pipe_configs == 2) { } else if (num_pipe_configs == 2) {
@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
gb_tile_moden = 0; gb_tile_moden = 0;
break; break;
} }
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
} }
} else } else

1
drivers/gpu/drm/radeon/radeon.h
View File

@ -1982,6 +1982,7 @@ struct cik_asic {
unsigned tile_config; unsigned tile_config;
uint32_t tile_mode_array[32]; uint32_t tile_mode_array[32];
uint32_t macrotile_mode_array[16];
}; };
union radeon_asic_config { union radeon_asic_config {

3
drivers/gpu/drm/radeon/radeon_drv.c
View File

@ -76,9 +76,10 @@
* 2.32.0 - new info request for rings working * 2.32.0 - new info request for rings working
* 2.33.0 - Add SI tiling mode array query * 2.33.0 - Add SI tiling mode array query
* 2.34.0 - Add CIK tiling mode array query * 2.34.0 - Add CIK tiling mode array query
* 2.35.0 - Add CIK macrotile mode array query
*/ */
#define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MAJOR 2
#define KMS_DRIVER_MINOR 34 #define KMS_DRIVER_MINOR 35
#define KMS_DRIVER_PATCHLEVEL 0 #define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev); int radeon_driver_unload_kms(struct drm_device *dev);

9
drivers/gpu/drm/radeon/radeon_kms.c
View File

@ -449,6 +449,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
return -EINVAL; return -EINVAL;
} }
break; break;
case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
if (rdev->family >= CHIP_BONAIRE) {
value = rdev->config.cik.macrotile_mode_array;
value_size = sizeof(uint32_t)*16;
} else {
DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
return -EINVAL;
}
break;
case RADEON_INFO_SI_CP_DMA_COMPUTE: case RADEON_INFO_SI_CP_DMA_COMPUTE:
*value = 1; *value = 1;
break; break;

2
include/uapi/drm/radeon_drm.h
View File

@ -981,6 +981,8 @@ struct drm_radeon_cs {
#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
/* query if CP DMA is supported on the compute ring */ /* query if CP DMA is supported on the compute ring */
#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
/* CIK macrotile mode array */
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
struct drm_radeon_info { struct drm_radeon_info {