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Merge branch 'marvell-cleanups'

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Weihang Li says:

====================
net: marvell: fix some coding style

Do some cleanups according to the coding style of kernel.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2021-03-29 13:23:59 -07:00
commit 32e67c0aea
4 changed files with 21 additions and 15 deletions
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6
drivers/net/ethernet/marvell/mv643xx_eth.c
View File

@ -700,7 +700,8 @@ static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
ip_hdr(skb)->ihl << TX_IHL_SHIFT; ip_hdr(skb)->ihl << TX_IHL_SHIFT;
/* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
* it seems we don't need to pass the initial checksum. */ * it seems we don't need to pass the initial checksum.
*/
switch (ip_hdr(skb)->protocol) { switch (ip_hdr(skb)->protocol) {
case IPPROTO_UDP: case IPPROTO_UDP:
cmd |= UDP_FRAME; cmd |= UDP_FRAME;
@ -790,7 +791,8 @@ txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
WARN(1, "failed to prepare checksum!"); WARN(1, "failed to prepare checksum!");
/* Should we set this? Can't use the value from skb_tx_csum() /* Should we set this? Can't use the value from skb_tx_csum()
* as it's not the correct initial L4 checksum to use. */ * as it's not the correct initial L4 checksum to use.
*/
desc->l4i_chk = 0; desc->l4i_chk = 0;
desc->byte_cnt = hdr_len; desc->byte_cnt = hdr_len;

12
drivers/net/ethernet/marvell/mvneta.c
View File

@ -1087,7 +1087,7 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
return 0; return 0;
} }
static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{ {
u32 wsize; u32 wsize;
u8 target, attr; u8 target, attr;
@ -3993,7 +3993,8 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
/* Armada 370 documentation says we can only change the port mode /* Armada 370 documentation says we can only change the port mode
* and in-band enable when the link is down, so force it down * and in-band enable when the link is down, so force it down
* while making these changes. We also do this for GMAC_CTRL2 */ * while making these changes. We also do this for GMAC_CTRL2
*/
if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
(new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
(new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
@ -4175,9 +4176,7 @@ static void mvneta_percpu_elect(struct mvneta_port *pp)
rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
if (cpu == elected_cpu) if (cpu == elected_cpu)
/* Map the default receive queue queue to the /* Map the default receive queue to the elected CPU */
* elected CPU
*/
rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
/* We update the TX queue map only if we have one /* We update the TX queue map only if we have one
@ -4907,7 +4906,8 @@ static int mvneta_ethtool_set_eee(struct net_device *dev,
u32 lpi_ctl0; u32 lpi_ctl0;
/* The Armada 37x documents do not give limits for this other than /* The Armada 37x documents do not give limits for this other than
* it being an 8-bit register. */ * it being an 8-bit register.
*/
if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
return -EINVAL; return -EINVAL;

9
drivers/net/ethernet/marvell/skge.c
View File

@ -1617,7 +1617,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
xm_write16(hw, port, XM_TX_THR, 512); xm_write16(hw, port, XM_TX_THR, 512);
/* /*
* Enable the reception of all error frames. This is is * Enable the reception of all error frames. This is
* a necessary evil due to the design of the XMAC. The * a necessary evil due to the design of the XMAC. The
* XMAC's receive FIFO is only 8K in size, however jumbo * XMAC's receive FIFO is only 8K in size, however jumbo
* frames can be up to 9000 bytes in length. When bad * frames can be up to 9000 bytes in length. When bad
@ -2959,8 +2959,9 @@ static void genesis_set_multicast(struct net_device *dev)
static void yukon_add_filter(u8 filter[8], const u8 *addr) static void yukon_add_filter(u8 filter[8], const u8 *addr)
{ {
u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
filter[bit/8] |= 1 << (bit%8);
filter[bit / 8] |= 1 << (bit % 8);
} }
static void yukon_set_multicast(struct net_device *dev) static void yukon_set_multicast(struct net_device *dev)
@ -3849,7 +3850,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
/* Only used for Genesis XMAC */ /* Only used for Genesis XMAC */
if (is_genesis(hw)) if (is_genesis(hw))
timer_setup(&skge->link_timer, xm_link_timer, 0); timer_setup(&skge->link_timer, xm_link_timer, 0);
else { else {
dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
NETIF_F_RXCSUM; NETIF_F_RXCSUM;

9
drivers/net/ethernet/marvell/sky2.c
View File

@ -55,7 +55,8 @@
#define RX_DEF_PENDING RX_MAX_PENDING #define RX_DEF_PENDING RX_MAX_PENDING
/* This is the worst case number of transmit list elements for a single skb: /* This is the worst case number of transmit list elements for a single skb:
VLAN:GSO + CKSUM + Data + skb_frags * DMA */ * VLAN:GSO + CKSUM + Data + skb_frags * DMA
*/
#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
#define TX_MIN_PENDING (MAX_SKB_TX_LE+1) #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
#define TX_MAX_PENDING 1024 #define TX_MAX_PENDING 1024
@ -1529,7 +1530,8 @@ static void sky2_rx_start(struct sky2_port *sky2)
sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
/* These chips have no ram buffer? /* These chips have no ram buffer?
* MAC Rx RAM Read is controlled by hardware */ * MAC Rx RAM Read is controlled by hardware
*/
if (hw->chip_id == CHIP_ID_YUKON_EC_U && if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
hw->chip_rev > CHIP_REV_YU_EC_U_A0) hw->chip_rev > CHIP_REV_YU_EC_U_A0)
sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
@ -4684,7 +4686,8 @@ static __exit void sky2_debug_cleanup(void)
#endif #endif
/* Two copies of network device operations to handle special case of /* Two copies of network device operations to handle special case of
not allowing netpoll on second port */ * not allowing netpoll on second port
*/
static const struct net_device_ops sky2_netdev_ops[2] = { static const struct net_device_ops sky2_netdev_ops[2] = {
{ {
.ndo_open = sky2_open, .ndo_open = sky2_open,